Module: Mesa Branch: master Commit: 3cf1d6b8db1287bf5e8647dfef21a58ff01750c1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cf1d6b8db1287bf5e8647dfef21a58ff01750c1
Author: Connor Abbott <[email protected]> Date: Fri Dec 20 15:16:54 2019 +0100 freedreno: Document CP_COND_REG_EXEC more The vulkan blob uses the RENDER_MODE mode to condition a blit on the render mode in traces of a dEQP triangle test. Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182> --- src/freedreno/registers/adreno_pm4.xml | 29 ++++++++++++++++++++++++++- src/freedreno/vulkan/tu_cmd_buffer.c | 8 ++++---- src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 16 +++++++-------- 3 files changed, 40 insertions(+), 13 deletions(-) diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml index 643d2b01b4c..3a1a0343767 100644 --- a/src/freedreno/registers/adreno_pm4.xml +++ b/src/freedreno/registers/adreno_pm4.xml @@ -1446,9 +1446,36 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) <!-- I *think* this existed at least as far back as a4xx --> <domain name="CP_COND_REG_EXEC" width="32"> + <enum name="compare_mode"> + <!-- use the predicate bit set by CP_REG_TEST --> + <value value="1" name="PRED_TEST"/> + <!-- compare two registers directly for equality --> + <value value="2" name="REG_COMPARE"/> + <!-- test if certain render modes are set via CP_SET_MARKER --> + <value value="3" name="RENDER_MODE" variants="A6XX-"/> + </enum> <reg32 offset="0" name="0"> - <bitfield name="UNK28" pos="28" type="boolean"/> + <bitfield name="REG0" low="0" high="17" type="hex"/> + + <!-- + Note: these bits have the same meaning, and use the same + internal mechanism as the bits in CP_SET_DRAW_STATE. + When RENDER_MODE is selected, they're used as + a bitmask of which modes pass the test. + --> + + <!-- RM6_BINNING --> + <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/> + <!-- all others --> + <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/> + <!-- RM6_BYPASS --> + <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/> + + <bitfield name="MODE" low="28" high="31" type="compare_mode"/> </reg32> + + <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 --> + <reg32 offset="1" name="1"> <bitfield name="DWORDS" low="0" high="31" type="uint"/> </reg32> diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index c18a0bd2438..f5f3f8739f0 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -702,8 +702,8 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd, A6XX_CP_REG_TEST_0_WAIT_FOR_ME); tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2); - tu_cs_emit(cs, 0x10000000); - tu_cs_emit(cs, 11); /* conditionally execute next 11 dwords */ + tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(11)); /* if (no overflow) */ { tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5, 7); @@ -1174,8 +1174,8 @@ emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs) A6XX_CP_REG_TEST_0_WAIT_FOR_ME); tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2); - tu_cs_emit(cs, 0x10000000); - tu_cs_emit(cs, 7); /* conditionally execute next 7 dwords */ + tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + tu_cs_emit(cs, CP_COND_REG_EXEC_1_DWORDS(7)); /* if (b0 set) */ { /* diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index e8f0992f310..74052baa5e1 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -462,8 +462,8 @@ emit_vsc_overflow_test(struct fd_batch *batch) A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 7); /* conditionally execute next 7 dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(7)); /* if (b0 set) */ { /* @@ -569,8 +569,8 @@ emit_conditional_ib(struct fd_batch *batch, struct fd_tile *tile, A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 4 * count); /* conditionally execute next 4*count dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(4 * count)); for (unsigned i = 0; i < count; i++) { uint32_t dwords; @@ -857,8 +857,8 @@ fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile) A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 11); /* conditionally execute next 11 dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(11)); /* if (no overflow) */ { OUT_PKT7(ring, CP_SET_BIN_DATA5, 7); @@ -1333,8 +1333,8 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile) A6XX_CP_REG_TEST_0_WAIT_FOR_ME); OUT_PKT7(ring, CP_COND_REG_EXEC, 2); - OUT_RING(ring, 0x10000000); - OUT_RING(ring, 2); /* conditionally execute next 2 dwords */ + OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST)); + OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(2)); /* if (no overflow) */ { OUT_PKT7(ring, CP_SET_MARKER, 1); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
