Module: Mesa Branch: master Commit: 2969012d03be1b0690eed6a855ffc57535c721eb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2969012d03be1b0690eed6a855ffc57535c721eb
Author: Jordan Justen <[email protected]> Date: Thu Jan 16 13:16:24 2020 -0800 anv: Emit CS Stall before Instruction Cache flush for gen12 WA Before flushing the instruction cache with a pipe control, we need to use a CS Stall pipe control. Ref: GEN:BUG:1409226450 Rework: Add stall-at-scoreboard (Lionel) Rework: Merge with other anvil pre-invalidate stalls (Lionel) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457> --- src/intel/vulkan/genX_cmd_buffer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index dbee6767414..0b6a78fcda8 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2022,6 +2022,12 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; } + /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which + * invalidates the instruction cache + */ + if (GEN_GEN == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)) + bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT; + if ((GEN_GEN >= 8 && GEN_GEN <= 9) && (bits & ANV_PIPE_CS_STALL_BIT) && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) { _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
