Module: Mesa Branch: master Commit: 73434b665b2ec50cbd1060ce831aec3b2e21517c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=73434b665b2ec50cbd1060ce831aec3b2e21517c
Author: Jason Ekstrand <[email protected]> Date: Fri Jan 17 11:23:14 2020 -0600 intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11 SML is no longer in the L3$ on Gen11+. It's not incredibly clear from the docs but no Gen11 platforms are in the list of platforms on which this bit exists. Also, we've been always setting it false on Gen11 in ANV and i965 thanks to GEN_L3P_SLM being zero with no ill effects. Cc: "20.0" [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454> --- src/gallium/drivers/iris/iris_state.c | 2 +- src/intel/genxml/gen11.xml | 1 - src/intel/vulkan/genX_cmd_buffer.c | 2 +- src/mesa/drivers/dri/i965/gen7_l3_state.c | 3 ++- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 6f277f08961..e3d7256dce9 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -747,7 +747,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg, #endif iris_pack_state(L3_ALLOCATION_REG, ®_val, reg) { -#if GEN_GEN < 12 +#if GEN_GEN < 11 reg.SLMEnable = has_slm; #endif #if GEN_GEN == 11 diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 3d5950d0efc..6d5ba940cda 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -6997,7 +6997,6 @@ </register> <register name="L3CNTLREG" length="1" num="0x7034"> - <field name="SLM Enable" start="0" end="0" type="uint"/> <field name="URB Allocation" start="1" end="7" type="uint"/> <field name="Error Detection Behavior Control" start="9" end="9" type="bool"/> <field name="Use Full Ways" start="10" end="10" type="bool"/> diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index aa31fb94d38..2b3c285d4a2 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1889,7 +1889,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, uint32_t l3cr; anv_pack_struct(&l3cr, L3_ALLOCATION_REG, -#if GEN_GEN < 12 +#if GEN_GEN < 11 .SLMEnable = has_slm, #endif #if GEN_GEN == 11 diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 3ee13d1e39f..feed3fab283 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -118,7 +118,8 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg) if (devinfo->gen >= 8) { assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]); - const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) | + const unsigned imm_data = ( + (devinfo->gen < 11 && has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) | (devinfo->gen == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) | SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) | SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) | _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
