Module: Mesa Branch: master Commit: 0905d5a14a790229c49914fc45e1dcd9d5c43c1d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0905d5a14a790229c49914fc45e1dcd9d5c43c1d
Author: Jason Ekstrand <[email protected]> Date: Wed Mar 4 11:09:50 2020 -0600 intel/isl: Don't align linear images to 64K on Gen12+ Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048> --- src/intel/isl/isl.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index e8889259cc7..95399002b40 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1651,10 +1651,19 @@ isl_surf_init_s(const struct isl_device *dev, */ if (tiling == ISL_TILING_GEN12_CCS) base_alignment_B = MAX(base_alignment_B, 4096); - } - if (ISL_DEV_GEN(dev) >= 12) { - base_alignment_B = MAX(base_alignment_B, 64 * 1024); + /* Gen12+ requires that images be 64K-aligned if they're going to used + * with CCS. This is because the Aux translation table maps main + * surface addresses to aux addresses at a 64K (in the main surface) + * granularity. Because we don't know for sure in ISL if a surface will + * use CCS, we have to guess based on the DISABLE_AUX usage bit. The + * one thing we do know is that we haven't enable CCS on linear images + * yet so we can avoid the extra alignment there. + */ + if (ISL_DEV_GEN(dev) >= 12 && + !(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) { + base_alignment_B = MAX(base_alignment_B, 64 * 1024); + } } if (ISL_DEV_GEN(dev) < 9) { _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
