URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73812999d92ed9812993f22a8807895d670fa4b8
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 23:12:38 2020 -0400
pan/bi: Pack BI_BLEND
MRT not yet supported to keep things easy.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Tested-by: Marge Bot
<https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4fb88723e74041b53d3dddda5b08f3ec94510b6
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 23:12:23 2020 -0400
pan/bi: Flesh out BI_BLEND
It ingests the output of ATEST, whatever that actually is.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e06426ea85fa9092e3488c9e4600181f534454b6
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 23:03:07 2020 -0400
pan/bi: Add ATEST packing
Only fp32 for now.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b18d0ef7081540b6c8d60bfd4f13792878ea1b28
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 23:02:12 2020 -0400
pan/bi: Flesh out ATEST in IR
ATEST actually takes two sources and has a destination. Although the
details are a little funny, we should still model this correctly.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=61260819ba3f08fccf72dfe7d7498516eec413f9
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 13:43:10 2020 -0400
pan/bi: Track clause types during scheduling
There's an easy mapping for this, so let's do it. Note we do this at
schedule-time instead of emit since we'll need to lookahead clause
types. The alternative is a prepass running after schedule but before
codegen, but there's no reason not to just stick it here when we're
preparing bi_clause in the first place.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e323df05a906aa91edfd4895627d28b6f9a12c6d
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 13:42:12 2020 -0400
pan/bi: Don't hide SCHED_ADD inside HI_LATENCY
It makes bitwise property checking annoying.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d797822d31c1a19580de6a357f96405f04ad916a
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 13:23:00 2020 -0400
pan/bi: Pretty-print clause types in disassembler
Also note that type=1 is for load_vary.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42af9f47c8a91caad6803fdaccf111053e9303c4
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 12:18:30 2020 -0400
pan/bi: Route through clause header
We already track almost all the information we need, let's dump it onto
the wire now.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4fbf751cfb863ee4b8e7963c0c37961519da774
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 12:08:28 2020 -0400
pan/bi: Skip over data registers in port assignment
They bypass the usual mechanism entirely, let's add some props to
describe this and respect them.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32e5a7e6e91b43105d51047cc315119928ff09ab
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 11:55:45 2020 -0400
pan/bi: Emit load_vary ops
Annoyingly long code to do so, but this should theoretically work for
both direct and indirect load_vary. Still need to handle destination.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=37f14c9e50ce144cc81bebf5124e7a9cd0ef0288
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 11:55:10 2020 -0400
pan/bi: Pass second src for load_vary ops
For direct, this is just 0, but for indirct, this is a sample mask
preloaded in R61. Handle this at code emit time instead of trying to do
crazy monkeypatching later.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=265169f48ada87fcea8e55dc4176954fb86d1153
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 11:54:25 2020 -0400
pan/bi: Generalize bi_get_src a bit
Allow it to work with ADD ops and stub out some immediate fetching
infrastructure (currently only works with 0).
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c0e786084f865d27b7be9d834855555fb0f049f
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 11:08:07 2020 -0400
pan/bi: List ADD classes in bi_pack_add
Handling will be... somewhat tricky.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6069904bbd46592d13a87520dc256c6006b12c50
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 11:02:57 2020 -0400
pan/bi: Pack fadd32
Choo choo.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2afcc6101047b8cfcd5fac3f144e1f3325e6207
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 09:58:59 2020 -0400
pan/bi: Pack BI_FMA ops
This is our first instruction we've emitted, requiring us to pipe
through registes/ports and various details from the IR. It's quite a bit
of code, but overall I'm happy with this structure. With some tedium we
should be able to emit the rest of the ALU ops this way, too.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a3bf3f1a1f13a6f14f849c5cdcdd1874566f88d
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 09:58:42 2020 -0400
pan/bi: Add struct bifrost_fma_fma
So we can pack regular FMA ops.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd40e189b6769f3cfb18557e3715a3289bebc13c
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 09:57:32 2020 -0400
pan/bi: Model 3-bit Bifrost srcs in IR
We'll want to set these manually for schedule-time passthrough, as well
as use the enum for packing.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe379776c7d7eca1bbb26af070710a1a2224b0ff
Author: Alyssa Rosenzweig <[email protected]>
Date: Wed Mar 18 09:22:58 2020 -0400
pan/bi: Route through first_instruction field
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90ca6a9a6b02087b97c12a6feb68381b41fa89d7
Author: Alyssa Rosenzweig <[email protected]>
Date: Tue Mar 17 23:01:48 2020 -0400
pan/bi: Assign registers to ports
Now that we can pack registers given the assigned ports, and we can
assign registers from the indices, the missing link is assigning ports
from the registers, and now finally we get some real data showing up in
a disassembly exercising lots of different code paths.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff39f57a48509f8a73655b6f4794cc5b73e4965c
Author: Alyssa Rosenzweig <[email protected]>
Date: Tue Mar 17 22:42:54 2020 -0400
pan/bi: Add missing __attribute__((packed))
That this code worked before makes me rather nervous...
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9080ea8b57817e385d157c623af1bde87841c304
Author: Alyssa Rosenzweig <[email protected]>
Date: Tue Mar 17 22:17:39 2020 -0400
pan/bi: Pack register fields
Now that we have ctrl, the rest is natural... sorta.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03a271bf15bd4aff587408be09066d2670ae47f8
Author: Alyssa Rosenzweig <[email protected]>
Date: Tue Mar 17 21:35:44 2020 -0400
pan/bi: Add packing for register control field
Filling in some gaps based on intuition from the bit patterns but this
should be vaguely right. More investigation needed down the line.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50bce53cd0c44db531b37cb37426e3b087c788da
Author: Alyssa Rosenzweig <[email protected]>
Date: Thu Mar 12 14:33:32 2020 -0400
pan/bi: Sketch out instruction word packing
Instructions are 78-bits with some seriously suspicious packing
requirements but hey, gotta save 'em bits.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9269c85578bd68169681efad0fb2a3563eb280ab
Author: Alyssa Rosenzweig <[email protected]>
Date: Thu Mar 12 14:16:22 2020 -0400
pan/bi: Setup initial clause packing
At the moment, we just iterate the clauses in the post-RA, post-sched IR
and generate a dummy clause corresponding, passing the results to the
disassembler to verify.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
_______________________________________________
mesa-commit mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
