Module: Mesa Branch: master Commit: 157a3cf3ecb6917c26508c5bf641e1b8c58e6228 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=157a3cf3ecb6917c26508c5bf641e1b8c58e6228
Author: Lionel Landwerlin <[email protected]> Date: Mon Oct 14 21:26:18 2019 +0300 isl: implement linear tiling row pitch requirement for display We're missing a requirement for alignment of row pitch for the display HW. In linear tiling, the row pitch must be a 64bytes aligned. v2: Use correct formula to align to 64bytes (Chad) v3: Matching {} (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243> --- src/intel/isl/isl.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 95399002b40..877dd8a1cdb 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1398,16 +1398,27 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev, */ const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format); const uint32_t bs = fmtl->bpb / 8; + uint32_t alignment; if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { if (isl_format_is_yuv(surf_info->format)) { - return 2 * bs; + alignment = 2 * bs; } else { - return bs; + alignment = bs; } + } else { + alignment = 1; } - return 1; + /* From the Broadwell PRM >> Volume 2c: Command Reference: Registers >> + * PRI_STRIDE Stride (p1254): + * + * "When using linear memory, this must be at least 64 byte aligned." + */ + if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) + alignment = isl_align(alignment, 64); + + return alignment; } static uint32_t _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
