Module: Mesa Branch: master Commit: afdb8e390787b8199a554a0fe688cc1150e4c58f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=afdb8e390787b8199a554a0fe688cc1150e4c58f
Author: Rob Clark <[email protected]> Date: Sat Mar 21 13:13:34 2020 -0700 freedreno/ir3: fix bogus register footprint with tess/gs When we have a tess or gs stage, VS outputs aren't normal varyings, so regid is r63.x.. we shouldn't extend our registerfootprint to 64! Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272> --- src/freedreno/ir3/ir3_shader.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c index c66330147e0..5ea6ba93902 100644 --- a/src/freedreno/ir3/ir3_shader.c +++ b/src/freedreno/ir3/ir3_shader.c @@ -96,6 +96,9 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id) } for (i = 0; i < v->outputs_count; i++) { + /* for ex, VS shaders with tess don't have normal varying outs: */ + if (!VALIDREG(v->outputs[i].regid)) + continue; int32_t regid = v->outputs[i].regid + 3; if (v->outputs[i].half) { if (gpu_id < 500) { _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
