Module: Mesa Branch: master Commit: 6da53911c15a33bf73fb1423b3e99affaceb0f75 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6da53911c15a33bf73fb1423b3e99affaceb0f75
Author: Rob Clark <[email protected]> Date: Mon Mar 23 08:58:07 2020 -0700 freedreno/ir3/ra: add debug option for RA debug msgs Similar to the debug switch for sched debug msgs Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272> --- src/freedreno/ir3/ir3_compiler.c | 4 +++- src/freedreno/ir3/ir3_compiler.h | 7 +++++-- src/freedreno/ir3/ir3_ra.c | 42 +++++++++++++++++++++++++++------------- 3 files changed, 37 insertions(+), 16 deletions(-) diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c index 7c762fffa28..3bb71c8942d 100644 --- a/src/freedreno/ir3/ir3_compiler.c +++ b/src/freedreno/ir3/ir3_compiler.c @@ -39,10 +39,12 @@ static const struct debug_named_value shader_debug_options[] = { {"optmsgs", IR3_DBG_OPTMSGS, "Enable optimizer debug messages"}, {"forces2en", IR3_DBG_FORCES2EN, "Force s2en mode for tex sampler instructions"}, {"nouboopt", IR3_DBG_NOUBOOPT, "Disable lowering UBO to uniform"}, + {"nofp16", IR3_DBG_NOFP16, "Don't lower mediump to fp16"}, #ifdef DEBUG + /* DEBUG-only options: */ {"schedmsgs", IR3_DBG_SCHEDMSGS, "Enable scheduler debug messages"}, + {"ramsgs", IR3_DBG_RAMSGS, "Enable register-allocation debug messages"}, #endif - {"nofp16", IR3_DBG_NOFP16, "Don't lower mediump to fp16"}, DEBUG_NAMED_VALUE_END }; diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h index 1a370ae2068..9b5307ed936 100644 --- a/src/freedreno/ir3/ir3_compiler.h +++ b/src/freedreno/ir3/ir3_compiler.h @@ -92,8 +92,11 @@ enum ir3_shader_debug { IR3_DBG_OPTMSGS = BITFIELD_BIT(7), IR3_DBG_FORCES2EN = BITFIELD_BIT(8), IR3_DBG_NOUBOOPT = BITFIELD_BIT(9), - IR3_DBG_SCHEDMSGS = BITFIELD_BIT(10), - IR3_DBG_NOFP16 = BITFIELD_BIT(11), + IR3_DBG_NOFP16 = BITFIELD_BIT(10), + + /* DEBUG-only options: */ + IR3_DBG_SCHEDMSGS = BITFIELD_BIT(20), + IR3_DBG_RAMSGS = BITFIELD_BIT(21), }; extern enum ir3_shader_debug ir3_shader_debug; diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c index 5f954ce2d94..215ce251f41 100644 --- a/src/freedreno/ir3/ir3_ra.c +++ b/src/freedreno/ir3/ir3_ra.c @@ -32,6 +32,21 @@ #include "ir3.h" #include "ir3_compiler.h" + +#ifdef DEBUG +#define RA_DEBUG (ir3_shader_debug & IR3_DBG_RAMSGS) +#else +#define RA_DEBUG 0 +#endif +#define d(fmt, ...) do { if (RA_DEBUG) { \ + printf("RA: "fmt"\n", ##__VA_ARGS__); \ +} } while (0) + +#define di(instr, fmt, ...) do { if (RA_DEBUG) { \ + printf("RA: "fmt": ", ##__VA_ARGS__); \ + ir3_print_instr(instr); \ +} } while (0) + /* * Register Assignment: * @@ -1097,7 +1112,7 @@ static void print_bitset(const char *name, BITSET_WORD *bs, unsigned cnt) { bool first = true; - debug_printf(" %s:", name); + debug_printf("RA: %s:", name); for (unsigned i = 0; i < cnt; i++) { if (BITSET_TEST(bs, i)) { if (!first) @@ -1131,34 +1146,35 @@ ra_add_interference(struct ir3_ra_ctx *ctx) /* update per-block livein/liveout: */ while (ra_compute_livein_liveout(ctx)) {} - if (ir3_shader_debug & IR3_DBG_OPTMSGS) { - debug_printf("AFTER LIVEIN/OUT:\n"); + if (RA_DEBUG) { + d("AFTER LIVEIN/OUT:"); foreach_block (block, &ir->block_list) { struct ir3_ra_block_data *bd = block->data; - debug_printf("block%u:\n", block_id(block)); + d("block%u:", block_id(block)); print_bitset(" def", bd->def, ctx->alloc_count); print_bitset(" use", bd->use, ctx->alloc_count); print_bitset(" l/i", bd->livein, ctx->alloc_count); print_bitset(" l/o", bd->liveout, ctx->alloc_count); } foreach_array (arr, &ir->array_list) { - debug_printf("array%u:\n", arr->id); - debug_printf(" length: %u\n", arr->length); - debug_printf(" start_ip: %u\n", arr->start_ip); - debug_printf(" end_ip: %u\n", arr->end_ip); + d("array%u:", arr->id); + d(" length: %u", arr->length); + d(" start_ip: %u", arr->start_ip); + d(" end_ip: %u", arr->end_ip); } - debug_printf("INSTRUCTION VREG NAMES:\n"); + d("INSTRUCTION VREG NAMES:"); foreach_block (block, &ctx->ir->block_list) { foreach_instr (instr, &block->instr_list) { if (!ctx->instrd[instr->ip].defn) continue; - debug_printf("%04u: ", scalar_name(ctx, instr, 0)); - ir3_print_instr(instr); + if (!writes_gpr(instr)) + continue; + di(instr, "%04u", scalar_name(ctx, instr, 0)); } } - debug_printf("ARRAY VREG NAMES:\n"); + d("ARRAY VREG NAMES:"); foreach_array (arr, &ctx->ir->array_list) { - debug_printf("%04u: arr%u\n", arr->base, arr->id); + d("%04u: arr%u", arr->base, arr->id); } } _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
