Module: Mesa Branch: master Commit: 6e7645347288c7dd8a4b95d69a4617278aa7b7c3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e7645347288c7dd8a4b95d69a4617278aa7b7c3
Author: Brian Ho <[email protected]> Date: Fri Apr 3 11:53:55 2020 -0700 ir3: Disable copy prop for immediate ldlw offsets Immediate offsets are currently collapsed for ldlw, but ldlw does behave correctly with immediate values. For example, `ldlw.u32 r0.x, l[4], 1` actually means to use the value of regid 4 (r1.x) as the offset when we actually want it to use the imm value of 4 as the offset. This commit disables copy prop for ldlw offsets so the same intrinsic gets compiled to: mov.u32u32 r0.y, 0x00000004 ldlw.u32 r0.x, l[r0.y], 1 Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4439> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4439> --- src/freedreno/ir3/ir3_cp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c index 14a5ae8d06c..5cac9c6b2d4 100644 --- a/src/freedreno/ir3/ir3_cp.c +++ b/src/freedreno/ir3/ir3_cp.c @@ -229,6 +229,9 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n, if (instr->opc == OPC_STLW && n == 0) return false; + if (instr->opc == OPC_LDLW && n == 0) + return false; + /* disallow CP into anything but the SSBO slot argument for * atomics: */ _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
