Hi Jerome, I was playing with this driver on my new machine (rv710) & was impressed with how well it worked. Unfortunately the next update everything went black...
I traced it down to this commit - it basically seems like all the vertex-buffer constants (at least) are ending up as zero, so most geometry doesn't get transformed properly. There are a few exceptions (like trivial/drawelements) which submit clip-space vertices & don't need transformation. I don't really know anything about how r600 hardware works, so thought I'd try & see if anyone else has an idea what's wrong... Keith On Thu, Sep 30, 2010 at 6:47 PM, Jerome Glisse <[email protected]> wrote: > Module: Mesa > Branch: master > Commit: 153105cfbfd8d6ff30de144605016f6e4f2a1b9e > URL: > http://cgit.freedesktop.org/mesa/mesa/commit/?id=153105cfbfd8d6ff30de144605016f6e4f2a1b9e > > Author: Jerome Glisse <[email protected]> > Date: Thu Sep 30 10:43:26 2010 -0400 > > r600g: use constant buffer instead of register for constant > > Signed-off-by: Jerome Glisse <[email protected]> > > --- > > src/gallium/drivers/r600/r600_state.c | 47 > +++++++++++-------------- > src/gallium/drivers/r600/r600d.h | 5 +++ > src/gallium/winsys/r600/drm/r600_hw_context.c | 34 +++--------------- > src/gallium/winsys/r600/drm/r600d.h | 5 +++ > 4 files changed, 36 insertions(+), 55 deletions(-) > > diff --git a/src/gallium/drivers/r600/r600_state.c > b/src/gallium/drivers/r600/r600_state.c > index 23323f1..23c2e59 100644 > --- a/src/gallium/drivers/r600/r600_state.c > +++ b/src/gallium/drivers/r600/r600_state.c > @@ -1148,41 +1148,35 @@ static void r600_set_constant_buffer(struct > pipe_context *ctx, uint shader, uint > struct pipe_resource *buffer) > { > struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; > - struct r600_pipe_state *rstate; > - struct pipe_transfer *transfer; > - unsigned *nconst = NULL; > - u32 *ptr, offset; > + struct r600_resource *rbuffer = (struct r600_resource*)buffer; > > switch (shader) { > case PIPE_SHADER_VERTEX: > - rstate = rctx->vs_const; > - nconst = &rctx->vs_nconst; > - offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000; > + rctx->vs_const_buffer.nregs = 0; > + r600_pipe_state_add_reg(&rctx->vs_const_buffer, > + R_028180_ALU_CONST_BUFFER_SIZE_VS_0, > + ALIGN_DIVUP(buffer->width0 >> 4, 16), > + 0xFFFFFFFF, NULL); > + r600_pipe_state_add_reg(&rctx->vs_const_buffer, > + R_028980_ALU_CONST_CACHE_VS_0, > + 0, 0xFFFFFFFF, rbuffer->bo); > + r600_context_pipe_state_set(&rctx->ctx, > &rctx->vs_const_buffer); > break; > case PIPE_SHADER_FRAGMENT: > - rstate = rctx->ps_const; > - nconst = &rctx->ps_nconst; > - offset = R_030000_SQ_ALU_CONSTANT0_0; > + rctx->ps_const_buffer.nregs = 0; > + r600_pipe_state_add_reg(&rctx->ps_const_buffer, > + R_028140_ALU_CONST_BUFFER_SIZE_PS_0, > + ALIGN_DIVUP(buffer->width0 >> 4, 16), > + 0xFFFFFFFF, NULL); > + r600_pipe_state_add_reg(&rctx->ps_const_buffer, > + R_028940_ALU_CONST_CACHE_PS_0, > + 0, 0xFFFFFFFF, rbuffer->bo); > + r600_context_pipe_state_set(&rctx->ctx, > &rctx->ps_const_buffer); > break; > default: > R600_ERR("unsupported %d\n", shader); > return; > } > - if (buffer && buffer->width0 > 0) { > - *nconst = buffer->width0 / 16; > - ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, > &transfer); > - if (ptr == NULL) > - return; > - for (int i = 0; i < *nconst; i++, offset += 0x10) { > - rstate[i].nregs = 0; > - r600_pipe_state_add_reg(&rstate[i], offset + 0x0, > ptr[i * 4 + 0], 0xFFFFFFFF, NULL); > - r600_pipe_state_add_reg(&rstate[i], offset + 0x4, > ptr[i * 4 + 1], 0xFFFFFFFF, NULL); > - r600_pipe_state_add_reg(&rstate[i], offset + 0x8, > ptr[i * 4 + 2], 0xFFFFFFFF, NULL); > - r600_pipe_state_add_reg(&rstate[i], offset + 0xC, > ptr[i * 4 + 3], 0xFFFFFFFF, NULL); > - r600_context_pipe_state_set(&rctx->ctx, &rstate[i]); > - } > - pipe_buffer_unmap(ctx, buffer, transfer); > - } > } > > static void *r600_create_shader_state(struct pipe_context *ctx, > @@ -1191,6 +1185,7 @@ static void *r600_create_shader_state(struct > pipe_context *ctx, > struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader); > int r; > > + shader->shader.use_mem_constant = TRUE; > r = r600_pipe_shader_create(ctx, shader, state->tokens); > if (r) { > return NULL; > @@ -1436,7 +1431,7 @@ void r600_init_config(struct r600_pipe_context *rctx) > tmp |= S_008C00_VC_ENABLE(1); > break; > } > - tmp |= S_008C00_DX9_CONSTS(1); > + tmp |= S_008C00_DX9_CONSTS(0); > tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); > tmp |= S_008C00_PS_PRIO(ps_prio); > tmp |= S_008C00_VS_PRIO(vs_prio); > diff --git a/src/gallium/drivers/r600/r600d.h > b/src/gallium/drivers/r600/r600d.h > index 47ab1eb..169cda5 100644 > --- a/src/gallium/drivers/r600/r600d.h > +++ b/src/gallium/drivers/r600/r600d.h > @@ -3484,6 +3484,11 @@ > #define R_038014_RESOURCE0_WORD5 0x038014 > #define R_038018_RESOURCE0_WORD6 0x038018 > > +#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140 > +#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180 > +#define R_028940_ALU_CONST_CACHE_PS_0 0x00028940 > +#define R_028980_ALU_CONST_CACHE_VS_0 0x00028980 > + > #define SQ_TEX_INST_LD 0x03 > #define SQ_TEX_INST_GET_GRADIENTS_H 0x7 > #define SQ_TEX_INST_GET_GRADIENTS_V 0x8 > diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c > b/src/gallium/winsys/r600/drm/r600_hw_context.c > index d1cf9e9..f363b69 100644 > --- a/src/gallium/winsys/r600/drm/r600_hw_context.c > +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c > @@ -253,6 +253,10 @@ static const struct r600_reg r600_context_reg_list[] = { > {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028124_CB_CLEAR_GREEN, 0, 0}, > {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028128_CB_CLEAR_BLUE, 0, 0}, > {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_02812C_CB_CLEAR_ALPHA, 0, 0}, > + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 0, 0}, > + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 0, 0}, > + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1)}, > + {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1)}, > {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_02823C_CB_SHADER_MASK, 0, 0}, > {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028238_CB_TARGET_MASK, 0, 0}, > {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028410_SX_ALPHA_TEST_CONTROL, 0, 0}, > @@ -479,23 +483,6 @@ static const struct r600_reg r600_context_reg_list[] = { > {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, > R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0}, > }; > > -/* SHADER CONSTANT R600/R700 */ > -static int r600_state_constant_init(struct r600_context *ctx, u32 offset) > -{ > - struct r600_reg r600_shader_constant[] = { > - {PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, > R_030000_SQ_ALU_CONSTANT0_0, 0, 0}, > - {PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, > R_030004_SQ_ALU_CONSTANT1_0, 0, 0}, > - {PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, > R_030008_SQ_ALU_CONSTANT2_0, 0, 0}, > - {PKT3_SET_ALU_CONST, R600_ALU_CONST_OFFSET, > R_03000C_SQ_ALU_CONSTANT3_0, 0, 0}, > - }; > - unsigned nreg = sizeof(r600_shader_constant)/sizeof(struct r600_reg); > - > - for (int i = 0; i < nreg; i++) { > - r600_shader_constant[i].offset += offset; > - } > - return r600_context_add_block(ctx, r600_shader_constant, nreg); > -} > - > /* SHADER RESOURCE R600/R700 */ > static int r600_state_resource_init(struct r600_context *ctx, u32 offset) > { > @@ -578,6 +565,7 @@ int r600_context_init(struct r600_context *ctx, struct > radeon *radeon) > int r; > > memset(ctx, 0, sizeof(struct r600_context)); > + radeon->use_mem_constant = TRUE; > ctx->radeon = radeon; > LIST_INITHEAD(&ctx->query_list); > > @@ -640,18 +628,6 @@ int r600_context_init(struct r600_context *ctx, struct > radeon *radeon) > if (r) > goto out_err; > } > - /* PS CONSTANT */ > - for (int j = 0, offset = 0; j < 256; j++, offset += 0x10) { > - r = r600_state_constant_init(ctx, offset); > - if (r) > - goto out_err; > - } > - /* VS CONSTANT */ > - for (int j = 0, offset = 0x1000; j < 256; j++, offset += 0x10) { > - r = r600_state_constant_init(ctx, offset); > - if (r) > - goto out_err; > - } > > /* setup block table */ > ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); > diff --git a/src/gallium/winsys/r600/drm/r600d.h > b/src/gallium/winsys/r600/drm/r600d.h > index fcce293..5c08c5a 100644 > --- a/src/gallium/winsys/r600/drm/r600d.h > +++ b/src/gallium/winsys/r600/drm/r600d.h > @@ -2200,4 +2200,9 @@ > #define R_038014_RESOURCE0_WORD5 0x038014 > #define R_038018_RESOURCE0_WORD6 0x038018 > > +#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140 > +#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180 > +#define R_028940_ALU_CONST_CACHE_PS_0 0x00028940 > +#define R_028980_ALU_CONST_CACHE_VS_0 0x00028980 > + > #endif > > _______________________________________________ > mesa-commit mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/mesa-commit > _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
