On Fri, 24 Jun 2011 12:42:50 -0700, Ben Widawsky <[email protected]> wrote: > Upload the system routine as part of the invariant state if debugging. > > Remove SIP setting if not debugging to make it more friendly for others > that may be debugging shaders or media kernels.
Instructions are from an offset of the brw->cache.bo these days. So you'd need to load the program data into there, and be careful to retain the SIP when brw_clear_cache() is called. > Signed-off-by: Ben Widawsky <[email protected]> > --- > src/mesa/drivers/dri/i965/brw_misc_state.c | 24 +++++++++++------------- > 1 files changed, 11 insertions(+), 13 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c > b/src/mesa/drivers/dri/i965/brw_misc_state.c > index 1f3b64f..2465bc0 100644 > --- a/src/mesa/drivers/dri/i965/brw_misc_state.c > +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c > @@ -633,19 +633,17 @@ static void upload_invarient_state( struct brw_context > *brw ) > } > } > } > - > - /* 0x61020000 State Instruction Pointer */ > - { > - struct brw_system_instruction_pointer sip; > - memset(&sip, 0, sizeof(sip)); > - > - sip.header.opcode = CMD_STATE_INSN_POINTER; > - sip.header.length = 0; > - sip.bits0.pad = 0; > - sip.bits0.system_instruction_pointer = 0; > - BRW_BATCH_STRUCT(brw, &sip); > - } > - > + /* The system routine must be set after a change to Instruction base */ > + if (brw->wm.debugging) { > + assert(brw->wm.system_routine != NULL); > + /* assert instruction base == 0 */ > + BEGIN_BATCH(4); > + OUT_BATCH(CMD_STATE_INSN_POINTER << 16); > + OUT_RELOC(brw->wm.system_routine, I915_GEM_DOMAIN_RENDER, 0, 0); > + OUT_BATCH(MI_FLUSH | 1 << 1); > + OUT_BATCH(MI_NOOP); > + ADVANCE_BATCH(); > + } > > { > struct brw_vf_statistics vfs; > -- > 1.7.5.2 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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