From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeonsi/si_state.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 4245452..9038704 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2240,9 +2240,8 @@ static void si_init_depth_surface(struct si_context *sctx,
z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
S_028040_ALLOW_EXPCLEAR(1);
- /* Use all of the htile_buffer for depth, because we don't
- * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
- s_info |= S_028044_TILE_STENCIL_DISABLE(1);
+ if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
+ s_info |= S_028044_TILE_STENCIL_DISABLE(1);
uint64_t va = rtex->htile_buffer->gpu_address;
db_htile_data_base = va >> 8;
@@ -3611,14 +3610,9 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
-
- /* There is a hang if stencil is used and fast stencil is enabled
- * regardless of whether HTILE is depth-only or not.
- */
si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
- S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
- S_02800C_FAST_STENCIL_DISABLE(1));
+ S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
--
2.1.4
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