Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Marek
On Mon, Mar 21, 2016 at 5:38 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haeh...@amd.com>
>
> This fixes arb_shader_image_load_store-host-mem-barrier.
>
> v2: flush TC L2 for index buffers on <= CIK (Marek)
> ---
> src/gallium/drivers/radeonsi/si_state.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index b9bdd47..3a490aa 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3536,18 +3536,28 @@ static void si_memory_barrier(struct pipe_context
> *ctx, unsigned flags)
> if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
> PIPE_BARRIER_SHADER_BUFFER |
> PIPE_BARRIER_TEXTURE |
> - PIPE_BARRIER_IMAGE)) {
> + PIPE_BARRIER_IMAGE |
> + PIPE_BARRIER_STREAMOUT_BUFFER)) {
> /* As far as I can tell, L1 contents are written back to L2
> * automatically at end of shader, but the contents of other
> * L1 caches might still be stale. */
> sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
> }
>
> + if (flags & PIPE_BARRIER_INDEX_BUFFER) {
> + sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
> +
> + /* Indices are read through TC L2 since VI. */
> + if (sctx->screen->b.chip_class <= CIK)
> + sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
> + }
> +
> if (flags & PIPE_BARRIER_FRAMEBUFFER)
> sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
>
> if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
> - PIPE_BARRIER_FRAMEBUFFER)) {
> + PIPE_BARRIER_FRAMEBUFFER |
> + PIPE_BARRIER_INDIRECT_BUFFER)) {
> /* Not sure if INV_GLOBAL_L2 is the best thing here.
> *
> * We need to make sure that TC L1 & L2 are written back to
> --
> 2.5.0
>
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