Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_clear.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 841ba5d..d57b677 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -239,6 +239,15 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
}
}
+ /* BLORP is currently only supported on Gen6+. */
+ if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) {
+ const bool encode_srgb = ctx->Color.sRGBEnabled;
+ if (brw_blorp_clear_color(brw, fb, mask, partial_clear, encode_srgb)) {
+ debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
+ mask &= ~BUFFER_BITS_COLOR;
+ }
+ }
+
/* Clear color buffers with fast clear or at least rep16 writes. */
if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) {
if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
--
2.5.5
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