On 21.04.2016 10:58, Marek Olšák wrote:
From: Marek Olšák <marek.ol...@amd.com>

this is a follow-up to the RW buffer cleanup.

Any chance you could squash this with the patch in the earlier series for better bisect-ability of the history? Either way,

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---
  src/gallium/drivers/radeonsi/si_descriptors.c | 42 ++++++++++++---------------
  1 file changed, 18 insertions(+), 24 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 343874c..6926c6b 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1226,33 +1226,27 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
                }
        }

-       /* Read/Write buffers. */
-       for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
+       /* Streamout buffers. (other internal buffers can't be invalidated) */
+       for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
                struct si_buffer_resources *buffers = &sctx->rw_buffers;
-               unsigned mask = buffers->desc.enabled_mask;

-               while (mask) {
-                       i = u_bit_scan(&mask);
-                       if (buffers->buffers[i] == buf) {
-                               si_desc_reset_buffer_offset(ctx, 
buffers->desc.list + i*4,
-                                                           old_va, buf);
-                               buffers->desc.dirty_mask |= 1u << i;
+               if (buffers->buffers[i] != buf)
+                       continue;

-                               radeon_add_to_buffer_list(&sctx->b, 
&sctx->b.gfx,
-                                                     rbuffer, 
buffers->shader_usage,
-                                                     buffers->priority);
-
-                               if (i >= SI_VS_STREAMOUT_BUF0 && shader == 
PIPE_SHADER_VERTEX) {
-                                       /* Update the streamout state. */
-                                       if (sctx->b.streamout.begin_emitted) {
-                                               
r600_emit_streamout_end(&sctx->b);
-                                       }
-                                       sctx->b.streamout.append_bitmask =
-                                               sctx->b.streamout.enabled_mask;
-                                       r600_streamout_buffers_dirty(&sctx->b);
-                               }
-                       }
-               }
+               si_desc_reset_buffer_offset(ctx, buffers->desc.list + i*4,
+                                           old_va, buf);
+               buffers->desc.dirty_mask |= 1u << i;
+
+               radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+                                         rbuffer, buffers->shader_usage,
+                                         buffers->priority);
+
+               /* Update the streamout state. */
+               if (sctx->b.streamout.begin_emitted)
+                       r600_emit_streamout_end(&sctx->b);
+               sctx->b.streamout.append_bitmask =
+                               sctx->b.streamout.enabled_mask;
+               r600_streamout_buffers_dirty(&sctx->b);
        }

        /* Constant and shader buffers. */

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