On 22.04.2016 17:19, Marek Olšák wrote: > On Fri, Apr 22, 2016 at 6:41 AM, Nicolai Hähnle <[email protected]> wrote: >> >> (Curiously, there is an old "this is probably not needed anymore" comment on >> the PS_PARTIAL_FLUSH in si_context_gfx_flush, but this may be wrong: since >> shaders can write memory, and the kernel may want to swap buffers around, we >> have to be extra careful about this...) > > PS_PARTIAL_FLUSH is not emitted in this case, because SURFACE_SYNC > does the same thing. > > Also, the kernel emits EVENT_WRITE_EOP(CACHE_FLUSH_AND_INV_TS_EVENT | > TC_ACTION_EN | TCL1_ACTION_EN) as part of the fence sequence, but it > doesn't wait. SI also flushes SMEM L1 and ICACHE before > EVENT_WRITE_EOP. The GPU scheduler waits for the fence when there is a > dependency (we can't have inter-process dependencies though). Memory > migrations always wait for idle.
Note that TTM BO migration always waits for idle due to a limitation of the current implementation, which may be lifted at some point. Not by design. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
