This lets the rest of the backend know that the uniform pull constant
load opcodes don't respect channel enables -- Without this the
register allocator has no way to know that the return payload of a
pull constant load is not per-channel and spills of the destination
will be broken under non-uniform control flow.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 ++
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index fd2ae96..0c806ee 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -2174,10 +2174,12 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
+ assert(inst->force_writemask_all);
generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
+ assert(inst->force_writemask_all);
generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 59a7a56..d550b13 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -3627,7 +3627,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
nir_intrinsic_instr *instr
while (remaining_components > 0) {
/* Read the vec4 from a 16-byte aligned offset */
struct brw_reg const_offset_reg = brw_imm_ud(const_offset_aligned);
- bld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
+ bld.exec_all()
+ .emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
retype(packed_consts, BRW_REGISTER_TYPE_F),
surf_index, const_offset_reg);
--
2.7.3
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