Are you sure this is Polaris-specific? I see a mention of this 14/30 as
well, but it seems to apply to all of gfx8.
The rest of this series is
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
On 24.06.2016 14:15, Marek Olšák wrote:
From: Marek Olšák <marek.ol...@amd.com>
ported from Vulkan (and no source explains why this is needed)
Cc: 12.0 <mesa-sta...@lists.freedesktop.org>
---
src/gallium/drivers/radeonsi/si_hw_context.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 3 ++-
src/gallium/drivers/radeonsi/si_state_draw.c | 19 +++++++++++++++++++
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index ec45d19..500eca7 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -240,6 +240,7 @@ void si_begin_new_cs(struct si_context *ctx)
ctx->last_ls_hs_config = -1;
ctx->last_rast_prim = -1;
ctx->last_sc_line_stipple = ~0;
+ ctx->last_vtx_reuse_depth = -1;
ctx->emit_scratch_reloc = true;
ctx->last_ls = NULL;
ctx->last_tcs = NULL;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 2e76483..fe92c6a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -303,6 +303,7 @@ struct si_context {
int last_ls_hs_config;
int last_rast_prim;
unsigned last_sc_line_stipple;
+ int last_vtx_reuse_depth;
int current_rast_prim; /* primitive type after TES,
GS */
unsigned last_gsvs_itemsize;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 7e09c8d..03a688c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3866,7 +3866,8 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
S_028424_OVERWRITE_COMBINER_WATERMARK(4));
- si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
+ if (sctx->b.family < CHIP_POLARIS10)
+ si_pm4_set_reg(pm4,
R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
vgt_tess_distribution =
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 641becf..616b604 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -438,6 +438,25 @@ static void si_emit_draw_registers(struct si_context *sctx,
unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
+ /* Polaris needs different VTX_REUSE_DEPTH settings depending on
+ * whether the "fractional odd" tessellation spacing is used.
+ */
+ if (sctx->b.family >= CHIP_POLARIS10) {
+ struct si_shader_selector *tes = sctx->tes_shader.cso;
+ unsigned vtx_reuse_depth = 30;
+
+ if (tes &&
+ tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
+ PIPE_TESS_SPACING_FRACTIONAL_ODD)
+ vtx_reuse_depth = 14;
+
+ if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
+ radeon_set_context_reg(cs,
R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
+ vtx_reuse_depth);
+ sctx->last_vtx_reuse_depth = vtx_reuse_depth;
+ }
+ }
+
if (sctx->tes_shader.cso)
si_emit_derived_tess_state(sctx, info, &num_patches);
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