+
+ nvc0->images_tic[stage][slot] =
+ gm107_create_texture_view_from_image(pipe, view);
+ tic = nv50_tic_entry(nvc0->images_tic[stage][slot]);
+
+ res = nv04_resource(tic->pipe.texture);
+ nvc0_update_tic(nvc0, tic, res);
+
+ if (tic->id < 0) {
+ tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
+
+ /* upload the texture view */
+ PUSH_SPACE(push, 16);
+ BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, txc->offset + (tic->id * 32));
+ PUSH_DATA (push, txc->offset + (tic->id * 32));
+ BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
+ PUSH_DATA (push, 32);
+ PUSH_DATA (push, 1);
+ BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), 9);
+ PUSH_DATA (push, 0x1001);
+ PUSH_DATAp(push, &tic->tic[0], 8);
+
+ BEGIN_NVC0(push, NVC0_3D(TIC_FLUSH), 1);
+ PUSH_DATA (push, 0);
+ } else
+ if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
+ BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
+ PUSH_DATA (push, (tic->id << 4) | 1);
+ }
+ nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+
+ res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
+
+ BCTX_REFN(nvc0->bufctx_3d, 3D_SUF, res, RD);
+
+ /* upload the texture handle */
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(stage));
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(stage));
+ BEGIN_NVC0(push, NVC0_3D(CB_POS), 2);
+ PUSH_DATA (push, NVC0_CB_AUX_TEX_INFO(slot + 32));
+ PUSH_DATA (push, tic->id);
+}
+
static inline void
nve4_update_surface_bindings(struct nvc0_context *nvc0)
{
@@ -1110,15 +1202,16 @@ nve4_update_surface_bindings(struct nvc0_context *nvc0)
if (!nvc0->images_dirty[s])
continue;
- BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
- PUSH_DATA (push, NVC0_CB_AUX_SIZE);
- PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
- PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
- BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 16 * NVC0_MAX_IMAGES);
- PUSH_DATA (push, NVC0_CB_AUX_SU_INFO(0));
-
for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
struct pipe_image_view *view = &nvc0->images[s][i];
+
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 16);
+ PUSH_DATA (push, NVC0_CB_AUX_SU_INFO(i));
+
if (view->resource) {
struct nv04_resource *res = nv04_resource(view->resource);
@@ -1129,6 +1222,9 @@ nve4_update_surface_bindings(struct nvc0_context *nvc0)
nve4_set_surface_info(push, view, nvc0);
BCTX_REFN(nvc0->bufctx_3d, 3D_SUF, res, RDWR);
+
+ if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
+ gm107_validate_surfaces(nvc0, view, s, i);
} else {
for (j = 0; j < 16; j++)
PUSH_DATA(push, 0);
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index 27301a1..3d32dfd 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
@@ -188,29 +188,99 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
}
static void
-nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
+gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
+ struct pipe_image_view *view, int slot)
{
+ struct nv04_resource *res = nv04_resource(view->resource);
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+ struct pipe_context *pipe = &nvc0->base.pipe;
+ struct nvc0_screen *screen = nvc0->screen;
+ struct nouveau_bo *txc = nvc0->screen->txc;
+ struct nv50_tic_entry *tic;
uint64_t address;
const int s = 5;
- int i, j;
- if (!nvc0->images_dirty[s])
- return;
+ if (nvc0->images_tic[s][slot])
+ pipe->sampler_view_destroy(pipe, nvc0->images_tic[s][slot]);
- address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
+ nvc0->images_tic[s][slot] =
+ gm107_create_texture_view_from_image(pipe, view);
+ tic = nv50_tic_entry(nvc0->images_tic[s][slot]);
+
+ res = nv04_resource(tic->pipe.texture);
+ nvc0_update_tic(nvc0, tic, res);
+
+ if (tic->id < 0) {
+ tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
+
+ /* upload the texture view */
+ PUSH_SPACE(push, 16);
+ BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, txc->offset + (tic->id * 32));
+ PUSH_DATA (push, txc->offset + (tic->id * 32));
+ BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
+ PUSH_DATA (push, 32);
+ PUSH_DATA (push, 1);
+ BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
+ PUSH_DATAp(push, &tic->tic[0], 8);
+
+ BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), 1);
+ PUSH_DATA (push, (tic->id << 4) | 1);
+ } else
+ if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
+ BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), 1);
+ PUSH_DATA (push, (tic->id << 4) | 1);
+ }
+ nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+
+ res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
+
+ BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
+ address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
+
+ /* upload the texture handle */
BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(0));
- PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(0));
+ PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
+ PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
- PUSH_DATA (push, 16 * NVC0_MAX_IMAGES * 4);
+ PUSH_DATA (push, 4);
PUSH_DATA (push, 0x1);
- BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16 * NVC0_MAX_IMAGES);
+ BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 2);
PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
+ PUSH_DATA (push, tic->id);
+
+ BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
+ PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
+}
+
+static void
+nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
+{
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+ uint64_t address;
+ const int s = 5;
+ int i, j;
+
+ if (!nvc0->images_dirty[s])
+ return;
+
+ address = nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
struct pipe_image_view *view = &nvc0->images[s][i];
+
+ BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, address + NVC0_CB_AUX_SU_INFO(i));
+ PUSH_DATA (push, address + NVC0_CB_AUX_SU_INFO(i));
+ BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
+ PUSH_DATA (push, 16 * 4);
+ PUSH_DATA (push, 0x1);
+ BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 16);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
+
if (view->resource) {
struct nv04_resource *res = nv04_resource(view->resource);
@@ -221,6 +291,9 @@ nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
nve4_set_surface_info(push, view, nvc0);
BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
+
+ if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
+ gm107_compute_validate_surfaces(nvc0, view, i);
} else {
for (j = 0; j < 16; j++)
PUSH_DATA(push, 0);
--
2.9.0
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