Thanks for hunting this down! Incidentally, it will get fixed by switching to blorp but we might as well merge it and fix it now.
On Wed, Aug 24, 2016 at 4:39 AM, Lionel Landwerlin <llandwer...@gmail.com> wrote: > Outside the shader, our actual tiling is Y0 which pitch is larger that > tiling W. Inside the shader we need to bring the pitch back to tiling W. > > Fixes dEQP-VK.api.copy_and_blit.image_to_image_stencil > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97448 > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > Cc: Jason Ekstrand <ja...@jlekstrand.net> > --- > src/intel/vulkan/anv_meta_blit2d.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/src/intel/vulkan/anv_meta_blit2d.c > b/src/intel/vulkan/anv_meta_blit2d.c > index 7085f2d..b0f17b7 100644 > --- a/src/intel/vulkan/anv_meta_blit2d.c > +++ b/src/intel/vulkan/anv_meta_blit2d.c > @@ -914,9 +914,12 @@ build_nir_w_tiled_fetch(struct nir_builder *b, struct > anv_device *device, > /* First, compute the block-aligned offset */ > nir_ssa_def *x_major = nir_ushr(b, x, nir_imm_int(b, 6)); > nir_ssa_def *y_major = nir_ushr(b, y, nir_imm_int(b, 6)); > + /* tex_pitch is expressed in terms of 128x32 Y tiled sizes. If we want > to > + * have W tiled offset, we need to bring that back to 64x64 tile sizes, > + * hence the multiplication by 32 (instead of 64). */ > I believe this is the correct change but not the correct comment. Really, what's going on is that W tiles have a "physical size" of 128x32 (same as a Y tile) and a logical size of 64x64. The calculation here needs to be using the physical size. > nir_ssa_def *offset = > nir_iadd(b, nir_imul(b, y_major, > - nir_imul(b, tex_pitch, nir_imm_int(b, 64))), > + nir_imul(b, tex_pitch, nir_imm_int(b, 32))), > nir_imul(b, x_major, nir_imm_int(b, 4096))); > > /* Compute the bottom 12 bits of the offset */ > -- > 2.9.3 > >
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