In the title did you mean GEN_1D?
Otherwise patches two and three look good also:
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
On Tue, Aug 23, 2016 at 09:53:48PM -0700, Jason Ekstrand wrote:
> If the surface has a layout of GEN4_2D then we need to compute a normal 2D
> alignment and not use the bogus 1D one.
>
> Signed-off-by: Jason Ekstrand <ja...@jlekstrand.net>
> Cc: Chad Versace <c...@kiwitree.net>
> ---
> src/intel/isl/isl_gen9.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c
> index cbbbba6..da8c749 100644
> --- a/src/intel/isl/isl_gen9.c
> +++ b/src/intel/isl/isl_gen9.c
> @@ -174,7 +174,7 @@ gen9_choose_image_alignment_el(const struct isl_device
> *dev,
> return;
> }
>
> - if (info->dim == ISL_SURF_DIM_1D) {
> + if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
> /* See the Skylake BSpec > Memory Views > Common Surface Formats >
> Surface
> * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
> */
> --
> 2.5.0.400.gff86faf
>
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