[Mesa-dev] [PATCH 17/20] radeonsi: also do VS_PARTIAL_FLUSH before updating VGT ring pointers

[Marek Olšák]

From: Marek Olšák <marek.ol...@amd.com>

ported from Vulkan
---
 src/gallium/drivers/radeonsi/si_state_shaders.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 394afaa..b4f19fe 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1602,20 +1602,26 @@ static void si_emit_spi_map(struct si_context *sctx, 
struct r600_atom *atom)
 }
 
 /**
  * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
  */
 static void si_init_config_add_vgt_flush(struct si_context *sctx)
 {
        if (sctx->init_config_has_vgt_flush)
                return;
 
+       /* Done by Vulkan before VGT_FLUSH. */
+       si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
+       si_pm4_cmd_add(sctx->init_config,
+                      EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+       si_pm4_cmd_end(sctx->init_config, false);
+
        /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
        si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
        si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | 
EVENT_INDEX(0));
        si_pm4_cmd_end(sctx->init_config, false);
        sctx->init_config_has_vgt_flush = true;
 }
 
 /* Initialize state related to ESGS / GSVS ring buffers */
 static bool si_update_gs_ring_buffers(struct si_context *sctx)
 {
-- 
2.7.4

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