For 9-14: Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Marek On Tue, Sep 13, 2016 at 11:56 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > From: Nicolai Hähnle <nicolai.haeh...@amd.com> > > Small buffers are now handled via the slabs code, so separate buckets in > pb_cache have become redundant. > --- > src/gallium/auxiliary/pipebuffer/pb_cache.h | 2 +- > src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 ++---- > src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 6 ++---- > 3 files changed, 5 insertions(+), 9 deletions(-) > > diff --git a/src/gallium/auxiliary/pipebuffer/pb_cache.h > b/src/gallium/auxiliary/pipebuffer/pb_cache.h > index aa83cc8..7000fcd 100644 > --- a/src/gallium/auxiliary/pipebuffer/pb_cache.h > +++ b/src/gallium/auxiliary/pipebuffer/pb_cache.h > @@ -43,21 +43,21 @@ struct pb_cache_entry > struct pb_cache *mgr; > int64_t start, end; /**< Caching time interval */ > unsigned bucket_index; > }; > > struct pb_cache > { > /* The cache is divided into buckets for minimizing cache misses. > * The driver controls which buffer goes into which bucket. > */ > - struct list_head buckets[8]; > + struct list_head buckets[4]; > > pipe_mutex mutex; > uint64_t cache_size; > uint64_t max_cache_size; > unsigned usecs; > unsigned num_buffers; > unsigned bypass_usage; > float size_factor; > > void (*destroy_buffer)(struct pb_buffer *buf); > diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c > b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c > index 6a61b30..ea8478f 100644 > --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c > +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c > @@ -734,26 +734,24 @@ no_slab: > */ > if (domain == RADEON_DOMAIN_VRAM_GTT) > usage = 1 << 2; > else > usage = domain >> 1; > assert(flags < sizeof(usage) * 8 - 3); > usage |= 1 << (flags + 3); > > /* Determine the pb_cache bucket for minimizing pb_cache misses. */ > pb_cache_bucket = 0; > - if (size <= 4096) /* small buffers */ > - pb_cache_bucket += 1; > if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ > - pb_cache_bucket += 2; > + pb_cache_bucket += 1; > if (flags == RADEON_FLAG_GTT_WC) /* WC */ > - pb_cache_bucket += 4; > + pb_cache_bucket += 2; > assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); > > /* Get a buffer from the cache. */ > bo = (struct amdgpu_winsys_bo*) > pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, usage, > pb_cache_bucket); > if (bo) > return &bo->base; > > /* Create a new one. */ > diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c > b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c > index 2e7635e..e6460ef 100644 > --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c > +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c > @@ -1007,26 +1007,24 @@ no_slab: > */ > if (domain == RADEON_DOMAIN_VRAM_GTT) > usage = 1 << 2; > else > usage = (unsigned)domain >> 1; > assert(flags < sizeof(usage) * 8 - 3); > usage |= 1 << (flags + 3); > > /* Determine the pb_cache bucket for minimizing pb_cache misses. */ > pb_cache_bucket = 0; > - if (size <= 4096) /* small buffers */ > - pb_cache_bucket += 1; > if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ > - pb_cache_bucket += 2; > + pb_cache_bucket += 1; > if (flags == RADEON_FLAG_GTT_WC) /* WC */ > - pb_cache_bucket += 4; > + pb_cache_bucket += 2; > assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); > > bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, > usage, pb_cache_bucket)); > if (bo) > return &bo->base; > > bo = radeon_create_bo(ws, size, alignment, usage, domain, flags, > pb_cache_bucket); > if (!bo) { > -- > 2.7.4 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev