One of the register we happen to program but don't have a description for
yet.

Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
---
 src/intel/genxml/gen6.xml  | 5 +++++
 src/intel/genxml/gen7.xml  | 5 +++++
 src/intel/genxml/gen75.xml | 5 +++++
 src/intel/genxml/gen8.xml  | 5 +++++
 src/intel/genxml/gen9.xml  | 5 +++++
 5 files changed, 25 insertions(+)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 52d0ecb..8fc02e0 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1968,4 +1968,9 @@
     <field name="System Instruction Pointer" start="36" end="63" 
type="offset"/>
   </instruction>
 
+  <register name="SO_WRITE_OFFSET" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
 </genxml>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 44bb2a7..a5a0571 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2521,6 +2521,11 @@
     <field name="SW Tessellation Memory Object Control State" start="40" 
end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>
 
+  <register name="SO_WRITE_OFFSET" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3SQCREG1" length="1" num="0xb010">
     <field name="Convert DC_UC" start="24" end="24" type="uint"/>
     <field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index b8f5a14..8db930e 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2919,6 +2919,11 @@
     <field name="SW Tessellation Memory Object Control State" start="40" 
end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>
 
+  <register name="SO_WRITE_OFFSET" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3SQCREG1" length="1" num="0xb010">
     <field name="Convert DC_UC" start="24" end="24" type="uint"/>
     <field name="Convert IS_UC" start="25" end="25" type="uint"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 5b2290e..1d5205f 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3166,6 +3166,11 @@
     <field name="SW Tessellation Memory Object Control State" start="40" 
end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
   </instruction>
 
+  <register name="SO_WRITE_OFFSET" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3CNTLREG" length="1" num="0x7034">
     <field name="SLM Enable" start="0" end="0" type="uint"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 547d47f..1a51032 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3440,6 +3440,11 @@
     <field name="System Instruction Pointer" start="36" end="95" 
type="offset"/>
   </instruction>
 
+  <register name="SO_WRITE_OFFSET" length="1" num="0x5280">
+    <field name="Write Offset" start="2" end="31" type="uint"/>
+    <field name="Reserved" start="0" end="1" type="uint"/>
+  </register>
+
   <register name="L3CNTLREG" length="1" num="0x7034">
     <field name="SLM Enable" start="0" end="0" type="uint"/>
     <field name="URB Allocation" start="1" end="7" type="uint"/>
-- 
2.9.3

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