On 13.10.2016 18:54, Marek Olšák wrote:
From: Marek Olšák <marek.ol...@amd.com>

Vulkan doesn't set these fields even though it doesn't use HiS.
HiS is disabled by programming DB_SRESULTS_COMPARE_STATEn to 0.

This probably has no effect, but it makes sense to handle state more similar to Vulkan in general.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---
 src/gallium/drivers/radeonsi/si_state.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index b23749c..732f9e9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3918,23 +3918,21 @@ static void si_init_config(struct si_context *sctx)
                       S_028230_ER_LINE_LR(0x1A) |
                       S_028230_ER_LINE_RL(0x26) |
                       S_028230_ER_LINE_TB(0xA) |
                       S_028230_ER_LINE_BT(0xA));
        /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
        si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
        si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
        si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
        si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
        si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
-       si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
-                      S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
-                      S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
+       si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);

        si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
        si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
        si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);

        if (sctx->b.chip_class >= CIK) {
                si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, 
S_00B51C_CU_EN(0xffff));
                si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
                si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, 
S_00B31C_CU_EN(0xffff));
                si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 
S_00B21C_CU_EN(0xffff));

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