From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/sid.h | 2 +-
src/gallium/drivers/radeon/r600_pipe_common.c | 4 ++--
src/gallium/drivers/radeon/r600_query.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 888de11..df6309c 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -7754,21 +7754,21 @@
#define V_028A90_VGT_STREAMOUT_SYNC 0x08
#define V_028A90_VGT_STREAMOUT_RESET 0x0A
#define V_028A90_END_OF_PIPE_INCR_DE 0x0B
#define V_028A90_END_OF_PIPE_IB_END 0x0C
#define V_028A90_RST_PIX_CNT 0x0D
#define V_028A90_VS_PARTIAL_FLUSH 0x0F
#define V_028A90_PS_PARTIAL_FLUSH 0x10
#define V_028A90_FLUSH_HS_OUTPUT 0x11
#define V_028A90_FLUSH_LS_OUTPUT 0x12
#define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
-#define V_028A90_ZPASS_DONE 0x15 /*
not on CIK */
+#define V_028A90_ZPASS_DONE 0x15
#define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16
#define V_028A90_PERFCOUNTER_START 0x17
#define V_028A90_PERFCOUNTER_STOP 0x18
#define V_028A90_PIPELINESTAT_START 0x19
#define V_028A90_PIPELINESTAT_STOP 0x1A
#define V_028A90_PERFCOUNTER_SAMPLE 0x1B
#define V_028A90_FLUSH_ES_OUTPUT 0x1C
#define V_028A90_FLUSH_GS_OUTPUT 0x1D
#define V_028A90_SAMPLE_PIPELINESTAT 0x1E
#define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 3dbcbc6..c4b70dc 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -87,30 +87,30 @@ void r600_gfx_write_fence(struct r600_common_context *ctx,
struct r600_resource
if (ctx->chip_class == CIK) {
/* Two EOP events are required to make all engines go idle
* (and optional cache flushes executed) before the timestamp
* is written.
*/
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
+ radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, old_value); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
+ radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, new_value); /* immediate data */
radeon_emit(cs, 0); /* unused */
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
RADEON_PRIO_QUERY);
}
unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
{
unsigned dwords = 6;
diff --git a/src/gallium/drivers/radeon/r600_query.c
b/src/gallium/drivers/radeon/r600_query.c
index 4b6767d..91385ae 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -553,21 +553,21 @@ static void r600_query_hw_do_emit_start(struct
r600_common_context *ctx,
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) |
EVENT_INDEX(3));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
case PIPE_QUERY_TIME_ELAPSED:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
+ radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
default:
@@ -639,21 +639,21 @@ static void r600_query_hw_do_emit_stop(struct
r600_common_context *ctx,
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
case PIPE_QUERY_TIME_ELAPSED:
va += 8;
/* fall through */
case PIPE_QUERY_TIMESTAMP:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
+ radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
fence_va = va + 8;
break;
case PIPE_QUERY_PIPELINE_STATISTICS: {
unsigned sample_size = (query->result_size - 8) / 2;
va += sample_size;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
--
2.7.4
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