From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 -
src/gallium/drivers/radeon/r600_texture.c | 2 --
src/gallium/drivers/radeonsi/si_state.c | 10 ++++++----
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index a33e290..941fc37 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -299,21 +299,20 @@ struct r600_texture {
unsigned num_slow_clears;
/* Counter that should be non-zero if the texture is bound to a
* framebuffer. Implemented in radeonsi only.
*/
uint32_t framebuffers_bound;
};
struct r600_surface {
struct pipe_surface base;
- const struct radeon_surf_level *level_info;
bool color_initialized;
bool depth_initialized;
/* Misc. color flags. */
bool alphatest_bypass;
bool export_16bpc;
bool color_is_int8;
/* Color registers. */
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index ff45261..6c8d5a7 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1749,37 +1749,35 @@ void vi_dcc_disable_if_incompatible_format(struct
r600_common_context *rctx,
if (!r600_texture_disable_dcc(rctx, (struct r600_texture*)tex))
rctx->decompress_dcc(&rctx->b, rtex);
}
struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface
*templ,
unsigned width, unsigned height)
{
struct r600_common_context *rctx = (struct r600_common_context*)pipe;
- struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
if (!surface)
return NULL;
assert(templ->u.tex.first_layer <= util_max_layer(texture,
templ->u.tex.level));
assert(templ->u.tex.last_layer <= util_max_layer(texture,
templ->u.tex.level));
pipe_reference_init(&surface->base.reference, 1);
pipe_resource_reference(&surface->base.texture, texture);
surface->base.context = pipe;
surface->base.format = templ->format;
surface->base.width = width;
surface->base.height = height;
surface->base.u = templ->u;
- surface->level_info = &rtex->surface.level[templ->u.tex.level];
if (texture->target != PIPE_BUFFER)
vi_dcc_disable_if_incompatible_format(rctx, texture,
templ->u.tex.level,
templ->format);
return &surface->base;
}
static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index ab3397c..642ce79 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2431,60 +2431,62 @@ static void si_emit_framebuffer_state(struct si_context
*sctx, struct r600_atom
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
unsigned i, nr_cbufs = state->nr_cbufs;
struct r600_texture *tex = NULL;
struct r600_surface *cb = NULL;
unsigned cb_color_info = 0;
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
+ const struct radeon_surf_level *level_info;
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
continue;
cb = (struct r600_surface*)state->cbufs[i];
if (!cb) {
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i
* 0x3C,
S_028C70_FORMAT(V_028C70_COLOR_INVALID));
continue;
}
tex = (struct r600_texture *)cb->base.texture;
+ level_info = &tex->surface.level[cb->base.u.tex.level];
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
&tex->resource, RADEON_USAGE_READWRITE,
tex->resource.b.b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
tex->cmask_buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_CMASK);
}
if (tex->dcc_separate_buffer)
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
tex->dcc_separate_buffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_DCC);
/* Compute mutable surface parameters. */
- pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
- slice_tile_max = cb->level_info->nblk_x *
- cb->level_info->nblk_y / 64 - 1;
+ pitch_tile_max = level_info->nblk_x / 8 - 1;
+ slice_tile_max = level_info->nblk_x *
+ level_info->nblk_y / 64 - 1;
tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level,
false);
- cb_color_base = (tex->resource.gpu_address +
cb->level_info->offset) >> 8;
+ cb_color_base = (tex->resource.gpu_address +
level_info->offset) >> 8;
cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
cb_color_attrib = cb->cb_color_attrib |
S_028C74_TILE_MODE_INDEX(tile_mode_index);
if (tex->fmask.size) {
if (sctx->b.chip_class >= CIK)
cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
cb_color_fmask = (tex->resource.gpu_address +
tex->fmask.offset) >> 8;
--
2.7.4
_______________________________________________
mesa-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
