From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeonsi/si_cp_dma.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index fb6ed26..45f20dd 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -168,31 +168,32 @@ static void si_cp_dma_prepare(struct si_context *sctx,
struct pipe_resource *dst
byte_count == remaining_size)
*packet_flags |= CP_DMA_SYNC;
}
static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource
*dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher)
{
struct si_context *sctx = (struct si_context*)ctx;
struct radeon_winsys *ws = sctx->b.ws;
+ struct r600_resource *rdst = r600_resource(dst);
unsigned tc_l2_flag = get_tc_l2_flag(sctx, coher);
unsigned flush_flags = get_flush_flags(sctx, coher);
bool is_first = true;
if (!size)
return;
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
* that range. */
- util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
+ util_range_add(&rdst->valid_buffer_range, offset,
offset + size);
/* Fallback for unaligned clears. */
if (offset % 4 != 0 || size % 4 != 0) {
uint8_t *map = sctx->b.ws->buffer_map(r600_resource(dst)->buf,
sctx->b.gfx.cs,
PIPE_TRANSFER_WRITE);
map += offset;
for (uint64_t i = 0; i < size; i++) {
unsigned byte_within_dword = (offset + i) % 4;
@@ -206,49 +207,48 @@ static void si_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
if (sctx->b.chip_class >= CIK && sctx->b.dma.cs &&
/* CP DMA is very slow. Always use SDMA for big clears. This
* alone improves DeusEx:MD performance by 70%. */
(size > 128 * 1024 ||
/* Buffers not used by the GFX IB yet will be cleared by SDMA.
* This happens to move most buffer clears to SDMA, including
* DCC and CMASK clears, because pipe->clear clears them before
* si_emit_framebuffer_state (in a draw call) adds them.
* For example, DeusEx:MD has 21 buffer clears per frame and all
* of them are moved to SDMA thanks to this. */
- !ws->cs_is_buffer_referenced(sctx->b.gfx.cs,
- r600_resource(dst)->buf,
+ !ws->cs_is_buffer_referenced(sctx->b.gfx.cs, rdst->buf,
RADEON_USAGE_READWRITE))) {
sctx->b.dma_clear_buffer(ctx, dst, offset, size, value);
return;
}
- uint64_t va = r600_resource(dst)->gpu_address + offset;
+ uint64_t va = rdst->gpu_address + offset;
/* Flush the caches. */
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
SI_CONTEXT_CS_PARTIAL_FLUSH | flush_flags;
while (size) {
unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
unsigned dma_flags = tc_l2_flag | CP_DMA_CLEAR;
si_cp_dma_prepare(sctx, dst, NULL, byte_count, size, 0,
&is_first, &dma_flags);
/* Emit the clear packet. */
si_emit_cp_dma(sctx, va, value, byte_count, dma_flags, coher);
size -= byte_count;
va += byte_count;
}
if (tc_l2_flag)
- r600_resource(dst)->TC_L2_dirty = true;
+ rdst->TC_L2_dirty = true;
/* If it's not a framebuffer fast clear... */
if (coher == R600_COHERENCY_SHADER)
sctx->b.num_cp_dma_calls++;
}
/**
* Realign the CP DMA engine. This must be done after a copy with an unaligned
* size.
*
--
2.7.4
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