On Tue, Jan 3, 2017 at 7:27 AM, Samuel Iglesias Gonsálvez <[email protected]> wrote: > Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> > --- > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > index 065e317..98e023a 100644 > --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > @@ -1208,6 +1208,15 @@ vec4_visitor::setup_imm_df(double v) > if (devinfo->gen >= 8) > return brw_imm_df(v); > > + /* gen7.5 does not support DF immediates straighforward but the DIM > + * instruction allows to set the 64-bit immediate value. > + */ > + if (devinfo->is_haswell) { > + dst_reg dst = retype(dst_reg(VGRF, alloc.allocate(2)), > BRW_REGISTER_TYPE_DF);
Does this need to be alloc.allocate(2)? Since we're just loading 64-bits worth of data, shouldn't one register be fine? If that is indeed okay, then with that change: Reviewed-by: Matt Turner <[email protected]> _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
