Reviewed-by: Bas Nieuwenhuizen <[email protected]> btw, isn't this enough already to export layer from the VS already? Might be useful for layered clears without GS.
On Mon, Jan 16, 2017 at 11:25 PM, Dave Airlie <[email protected]> wrote: > From: Dave Airlie <[email protected]> > > This just adds the infrastructure to allow writing layer > and viewport index. It's just a first patch out of the geom > shader tree, and doesn't do much on its own. > > v2: add missing if statement change (Bas) > > Signed-off-by: Dave Airlie <[email protected]> > --- > src/amd/common/ac_nir_to_llvm.c | 21 ++++++++++++++++++--- > src/amd/common/ac_nir_to_llvm.h | 2 ++ > src/amd/vulkan/radv_cmd_buffer.c | 6 +++++- > 3 files changed, 25 insertions(+), 4 deletions(-) > > diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c > index 798ddca..3173aa5 100644 > --- a/src/amd/common/ac_nir_to_llvm.c > +++ b/src/amd/common/ac_nir_to_llvm.c > @@ -4107,7 +4107,7 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx) > unsigned pos_idx, num_pos_exports = 0; > LLVMValueRef args[9]; > LLVMValueRef pos_args[4][9] = { { 0 } }; > - LLVMValueRef psize_value = 0; > + LLVMValueRef psize_value = NULL, layer_value = NULL, > viewport_index_value = NULL; > int i; > const uint64_t clip_mask = ctx->output_mask & ((1ull << > VARYING_SLOT_CLIP_DIST0) | > (1ull << > VARYING_SLOT_CLIP_DIST1) | > @@ -4167,6 +4167,14 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx) > ctx->shader_info->vs.writes_pointsize = true; > psize_value = values[0]; > continue; > + } else if (i == VARYING_SLOT_LAYER) { > + ctx->shader_info->vs.writes_layer = true; > + layer_value = values[0]; > + continue; > + } else if (i == VARYING_SLOT_VIEWPORT) { > + ctx->shader_info->vs.writes_viewport_index = true; > + viewport_index_value = values[0]; > + continue; > } else if (i >= VARYING_SLOT_VAR0) { > ctx->shader_info->vs.export_mask |= 1u << (i - > VARYING_SLOT_VAR0); > target = V_008DFC_SQ_EXP_PARAM + param_count; > @@ -4200,8 +4208,11 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx) > pos_args[0][8] = ctx->f32one; /* W */ > } > > - if (ctx->shader_info->vs.writes_pointsize == true) { > - pos_args[1][0] = LLVMConstInt(ctx->i32, > (ctx->shader_info->vs.writes_pointsize == true), false); /* writemask */ > + uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : > 0) | > + (ctx->shader_info->vs.writes_layer == true ? 4 : 0) | > + (ctx->shader_info->vs.writes_viewport_index == true > ? 8 : 0)); > + if (mask) { > + pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* > writemask */ > pos_args[1][1] = ctx->i32zero; /* EXEC mask */ > pos_args[1][2] = ctx->i32zero; /* last export? */ > pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + > 1, false); > @@ -4213,6 +4224,10 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx) > > if (ctx->shader_info->vs.writes_pointsize == true) > pos_args[1][5] = psize_value; > + if (ctx->shader_info->vs.writes_layer == true) > + pos_args[1][7] = layer_value; > + if (ctx->shader_info->vs.writes_viewport_index == true) > + pos_args[1][8] = viewport_index_value; > } > for (i = 0; i < 4; i++) { > if (pos_args[i][0]) > diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h > index f488c09..a57558e 100644 > --- a/src/amd/common/ac_nir_to_llvm.h > +++ b/src/amd/common/ac_nir_to_llvm.h > @@ -95,6 +95,8 @@ struct ac_shader_variant_info { > unsigned vgpr_comp_cnt; > uint32_t export_mask; > bool writes_pointsize; > + bool writes_layer; > + bool writes_viewport_index; > uint8_t clip_dist_mask; > uint8_t cull_dist_mask; > } vs; > diff --git a/src/amd/vulkan/radv_cmd_buffer.c > b/src/amd/vulkan/radv_cmd_buffer.c > index 01e77f8..27fa405 100644 > --- a/src/amd/vulkan/radv_cmd_buffer.c > +++ b/src/amd/vulkan/radv_cmd_buffer.c > @@ -500,7 +500,11 @@ radv_emit_vertex_shader(struct radv_cmd_buffer > *cmd_buffer, > > radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL, > > S_02881C_USE_VTX_POINT_SIZE(vs->info.vs.writes_pointsize) | > - > S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize) | > + > S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->info.vs.writes_layer) | > + > S_02881C_USE_VTX_VIEWPORT_INDX(vs->info.vs.writes_viewport_index) | > + > S_02881C_VS_OUT_MISC_VEC_ENA(vs->info.vs.writes_pointsize || > + > vs->info.vs.writes_layer || > + > vs->info.vs.writes_viewport_index) | > S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & > 0x0f) != 0) | > S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & > 0xf0) != 0) | > pipeline->graphics.raster.pa_cl_vs_out_cntl | > -- > 2.9.3 > > _______________________________________________ > mesa-dev mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
