Everything should be ready to go on maxwell as well, but the sched code
calculator ends up causing a lot of failures with the generated code.
Since this is a fringe feature, leave it out until the sched code logic
is improved.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
---
docs/features.txt | 2 +-
docs/relnotes/17.1.0.html | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ++-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index 2f2d41d..95b6e2c 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -283,7 +283,7 @@ Khronos, ARB, and OES extensions that are not part of any
OpenGL or OpenGL ES ve
GL_ARB_ES3_2_compatibility DONE (i965/gen8+)
GL_ARB_fragment_shader_interlock not started
GL_ARB_gl_spirv not started
- GL_ARB_gpu_shader_int64 DONE (i965/gen8+,
radeonsi, softpipe, llvmpipe)
+ GL_ARB_gpu_shader_int64 DONE (i965/gen8+,
nvc0, radeonsi, softpipe, llvmpipe)
GL_ARB_indirect_parameters DONE (nvc0, radeonsi)
GL_ARB_parallel_shader_compile not started, but
Chia-I Wu did some related work in 2014
GL_ARB_pipeline_statistics_query DONE (i965, nvc0,
radeonsi, softpipe, swr)
diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
index e9f08f8..041a1e6 100644
--- a/docs/relnotes/17.1.0.html
+++ b/docs/relnotes/17.1.0.html
@@ -44,7 +44,7 @@ Note: some of the new features are only available with
certain drivers.
</p>
<ul>
-<li>GL_ARB_gpu_shader_int64 on i965/gen8+, radeonsi, softpipe, llvmpipe</li>
+<li>GL_ARB_gpu_shader_int64 on i965/gen8+, nvc0, radeonsi, softpipe,
llvmpipe</li>
</ul>
<h2>Bug fixes</h2>
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index e99dc4c..c482c3e 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -253,6 +253,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
case PIPE_CAP_TGSI_FS_FBFETCH:
return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
+ case PIPE_CAP_INT64:
+ return class_3d < GM107_3D_CLASS;
/* unsupported caps */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@@ -281,7 +283,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
- case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
return 0;
--
2.10.2
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