On Fri, 18 Nov 2011 15:41:04 -0800, Chad Versace <chad.vers...@linux.intel.com>
wrote:
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> On 11/18/2011 03:24 PM, Eric Anholt wrote:
> > On Thu, 17 Nov 2011 19:58:44 -0800, Chad Versace
> > <chad.vers...@linux.intel.com> wrote:
> >> +bool
> >> +intel_miptree_alloc_hiz(struct intel_context *intel,
> >> + struct intel_mipmap_tree *mt)
> >> +{
> >> + assert(mt->hiz_mt == NULL);
> >> + mt->hiz_mt = intel_miptree_create(intel,
> >> + mt->target,
> >> + MESA_FORMAT_X8_Z24,
> >> + mt->first_level,
> >> + mt->last_level,
> >> + mt->width0,
> >> + mt->height0,
> >> + mt->depth0,
> >> + true);
> >> + return mt->hiz_mt != NULL;
> >> +}
> >
> > We don't get any size reduction on the hiz miptree compared to the real
> > miptree?
>
> Yes and no.
>
> No, because we always set LOD=0 and manually compute the draw offsets in
> the SURFACE_STATE batch. The HiZ and stencil buffers inherit the draw
> offset from 3DSTATE_DEPTH_BUFFER, so the HiZ and stencil miptree must have
> identical layout to the depth miptree.
>
> To save memory, we could waiver the identical-layout requirement and allocate
> a small hiz and stencil miptrees for non-texture renderbuffers, since the draw
> offsets will never be used in that case. But let's save that optimization for
> a future patch.
>
> Yes, we could allocate small hiz and stencil miptrees if (and that's a big if)
> we used the LOD field in SURFACE_STATE. The hardware expects compact miptree
> layout in that case.Good enough answer for me.
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