On Mon, Mar 13, 2017 at 03:27:58PM -0700, Chad Versace wrote: > isl has a giant comment that explains the hardware's padding > requirements. (Hint: Cache lines and page faults). But the comment is in > the wrong place, in isl_calc_linear_row_pitch(), which is unrelated to > padding. > > The important parts of that comment were copied to > isl_apply_surface_padding() long ago. So drop the misplaced comment. > --- > src/intel/isl/isl.c | 46 ---------------------------------------------- > 1 file changed, 46 deletions(-)
This patch is Reviewed-by: Nanley Chery <[email protected]> > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c > index 6eb1e93efd9..ebc8d84be0f 100644 > --- a/src/intel/isl/isl.c > +++ b/src/intel/isl/isl.c > @@ -1004,53 +1004,7 @@ isl_calc_linear_row_pitch(const struct isl_device *dev, > const struct isl_extent2d *phys_slice0_sa) > { > const struct isl_format_layout *fmtl = > isl_format_get_layout(info->format); > - > uint32_t row_pitch = info->min_pitch; > - > - /* First, align the surface to a cache line boundary, as the PRM explains > - * below. > - * > - * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface > - * Formats >> Surface Padding Requirements >> Render Target and Media > - * Surfaces: > - * > - * The data port accesses data (pixels) outside of the surface if they > - * are contained in the same cache request as pixels that are within > the > - * surface. These pixels will not be returned by the requesting > message, > - * however if these pixels lie outside of defined pages in the GTT, > - * a GTT error will result when the cache request is processed. In > order > - * to avoid these GTT errors, “padding” at the bottom of the surface is > - * sometimes necessary. > - * > - * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface > - * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: > - * > - * The sampling engine accesses texels outside of the surface if they > - * are contained in the same cache line as texels that are within the > - * surface. These texels will not participate in any calculation > - * performed by the sampling engine and will not affect the result of > - * any sampling engine operation, however if these texels lie outside > of > - * defined pages in the GTT, a GTT error will result when the cache > line > - * is accessed. In order to avoid these GTT errors, “padding” at the > - * bottom and right side of a sampling engine surface is sometimes > - * necessary. > - * > - * It is possible that a cache line will straddle a page boundary if > the > - * base address or pitch is not aligned. All pages included in the > cache > - * lines that are part of the surface must map to valid GTT entries to > - * avoid errors. To determine the necessary padding on the bottom and > - * right side of the surface, refer to the table in Alignment Unit > Size > - * section for the i and j parameters for the surface format in use. > The > - * surface must then be extended to the next multiple of the alignment > - * unit size in each dimension, and all texels contained in this > - * extended surface must have valid GTT entries. > - * > - * For example, suppose the surface size is 15 texels by 10 texels and > - * the alignment parameters are i=4 and j=2. In this case, the extended > - * surface would be 16 by 10. Note that these calculations are done in > - * texels, and must be converted to bytes based on the surface format > - * being used to determine whether additional pages need to be defined. > - */ > assert(phys_slice0_sa->w % fmtl->bw == 0); > const uint32_t bs = fmtl->bpb / 8; > row_pitch = MAX(row_pitch, bs * (phys_slice0_sa->w / fmtl->bw)); > -- > 2.12.0 > > _______________________________________________ > mesa-dev mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
