On Thu, Mar 16, 2017 at 3:24 AM, Lionel Landwerlin < [email protected]> wrote:
> I might be wrong, but are you sure it's a good idea? > > The documentation says that dword0 is the lower 32bits of a qword and > dword1 the upper bits. > With this change we now make it look like it's a regular 64 bits number > but it actually isn't. > I'm not sure what you mean. If you're doing a 64-bit store, the packing structs will put the lower 32 bits in dword0 and the upper 32 bits in dword1 just like you want. There are a number of other hardware packets that split a 64-bit value into two 32-bit values for no good reason other than that the bspec likes to talk about dwords. A bunch of those have gotten similar treatment over time. > > On 16/03/17 00:03, Jason Ekstrand wrote: > >> This is way more convenient than having two separate dword fields. >> --- >> src/intel/genxml/gen6.xml | 3 +-- >> src/intel/genxml/gen7.xml | 3 +-- >> src/intel/genxml/gen75.xml | 3 +-- >> src/intel/genxml/gen8.xml | 3 +-- >> src/intel/genxml/gen9.xml | 3 +-- >> src/intel/vulkan/genX_query.c | 3 +-- >> 6 files changed, 6 insertions(+), 12 deletions(-) >> >> diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml >> index 6a9b090..8a7eee0 100644 >> --- a/src/intel/genxml/gen6.xml >> +++ b/src/intel/genxml/gen6.xml >> @@ -1805,8 +1805,7 @@ >> <field name="DWord Length" start="0" end="5" type="uint" >> default="2"/> >> <field name="Address" start="66" end="95" type="address"/> >> <field name="Core Mode Enable" start="64" end="64" type="uint"/> >> - <field name="Data DWord 0" start="96" end="127" type="uint"/> >> - <field name="Data DWord 1" start="128" end="159" type="uint"/> >> + <field name="Immediate Data" start="96" end="159" type="uint"/> >> </instruction> >> <instruction name="MI_STORE_DATA_INDEX" bias="2" length="3"> >> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml >> index 7368b5b..8219d64 100644 >> --- a/src/intel/genxml/gen7.xml >> +++ b/src/intel/genxml/gen7.xml >> @@ -2316,8 +2316,7 @@ >> <field name="DWord Length" start="0" end="5" type="uint" >> default="2"/> >> <field name="Address" start="66" end="95" type="address"/> >> <field name="Core Mode Enable" start="64" end="64" type="uint"/> >> - <field name="Data DWord 0" start="96" end="127" type="uint"/> >> - <field name="Data DWord 1" start="128" end="159" type="uint"/> >> + <field name="Immediate Data" start="96" end="159" type="uint"/> >> </instruction> >> <instruction name="MI_STORE_DATA_INDEX" bias="2" length="3"> >> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml >> index ed82236..8e65c59 100644 >> --- a/src/intel/genxml/gen75.xml >> +++ b/src/intel/genxml/gen75.xml >> @@ -2709,8 +2709,7 @@ >> <field name="DWord Length" start="0" end="5" type="uint" >> default="2"/> >> <field name="Address" start="66" end="95" type="address"/> >> <field name="Core Mode Enable" start="64" end="64" type="uint"/> >> - <field name="Data DWord 0" start="96" end="127" type="uint"/> >> - <field name="Data DWord 1" start="128" end="159" type="uint"/> >> + <field name="Immediate Data" start="96" end="159" type="uint"/> >> </instruction> >> <instruction name="MI_STORE_DATA_INDEX" bias="2" length="3"> >> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml >> index 32ed764..1628237 100644 >> --- a/src/intel/genxml/gen8.xml >> +++ b/src/intel/genxml/gen8.xml >> @@ -2980,8 +2980,7 @@ >> <field name="DWord Length" start="0" end="9" type="uint" >> default="2"/> >> <field name="Address" start="34" end="79" type="address"/> >> <field name="Core Mode Enable" start="32" end="32" type="uint"/> >> - <field name="Data DWord 0" start="96" end="127" type="uint"/> >> - <field name="Data DWord 1" start="128" end="159" type="uint"/> >> + <field name="Immediate Data" start="96" end="159" type="uint"/> >> </instruction> >> <instruction name="MI_STORE_DATA_INDEX" bias="2" length="3"> >> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml >> index ec29d13..6849669 100644 >> --- a/src/intel/genxml/gen9.xml >> +++ b/src/intel/genxml/gen9.xml >> @@ -3255,8 +3255,7 @@ >> <field name="DWord Length" start="0" end="9" type="uint" >> default="2"/> >> <field name="Address" start="34" end="79" type="address"/> >> <field name="Core Mode Enable" start="32" end="32" type="uint"/> >> - <field name="Data DWord 0" start="96" end="127" type="uint"/> >> - <field name="Data DWord 1" start="128" end="159" type="uint"/> >> + <field name="Immediate Data" start="96" end="159" type="uint"/> >> </instruction> >> <instruction name="MI_STORE_DATA_INDEX" bias="2" length="3"> >> diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query. >> c >> index b5955d3..2429386 100644 >> --- a/src/intel/vulkan/genX_query.c >> +++ b/src/intel/vulkan/genX_query.c >> @@ -243,8 +243,7 @@ void genX(CmdResetQueryPool)( >> .offset = (firstQuery + i) * sizeof(struct >> anv_query_pool_slot) + >> offsetof(struct anv_query_pool_slot, >> available), >> }; >> - sdm.DataDWord0 = 0; >> - sdm.DataDWord1 = 0; >> + sdm.ImmediateData = 0; >> } >> break; >> } >> > > >
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