From: Marek Olšák <marek.ol...@amd.com>
Add _GFX6 and _GFX9 suffixes to conflicting definitions.
sid.h and gfx9d.h can now be included in the same file.
---
src/amd/common/gfx9d.h | 60 +++++++++++++--------------
src/amd/common/sid.h | 60 +++++++++++++--------------
src/gallium/drivers/radeonsi/si_descriptors.c | 4 +-
src/gallium/drivers/radeonsi/si_state.c | 2 +-
4 files changed, 63 insertions(+), 63 deletions(-)
diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index fa4e4cd..702508b 100644
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -1332,23 +1332,23 @@
#define S_008F1C_SW_MODE(x)
(((unsigned)(x) & 0x1F) << 20)
#define G_008F1C_SW_MODE(x) (((x) >>
20) & 0x1F)
#define C_008F1C_SW_MODE
0xFE0FFFFF
#define S_008F1C_TYPE(x)
(((unsigned)(x) & 0x0F) << 28)
#define G_008F1C_TYPE(x) (((x) >>
28) & 0x0F)
#define C_008F1C_TYPE
0x0FFFFFFF
#define R_008F20_SQ_IMG_RSRC_WORD4
0x008F20
#define S_008F20_DEPTH(x)
(((unsigned)(x) & 0x1FFF) << 0)
#define G_008F20_DEPTH(x) (((x) >>
0) & 0x1FFF)
#define C_008F20_DEPTH
0xFFFFE000
-#define S_008F20_PITCH(x)
(((unsigned)(x) & 0xFFFF) << 13)
-#define G_008F20_PITCH(x) (((x) >>
13) & 0xFFFF)
-#define C_008F20_PITCH
0xE0001FFF
+#define S_008F20_PITCH_GFX9(x)
(((unsigned)(x) & 0xFFFF) << 13)
+#define G_008F20_PITCH_GFX9(x) (((x) >>
13) & 0xFFFF)
+#define C_008F20_PITCH_GFX9
0xE0001FFF
#define S_008F20_BC_SWIZZLE(x)
(((unsigned)(x) & 0x07) << 29)
#define G_008F20_BC_SWIZZLE(x) (((x) >>
29) & 0x07)
#define C_008F20_BC_SWIZZLE
0x1FFFFFFF
#define R_008F24_SQ_IMG_RSRC_WORD5
0x008F24
#define S_008F24_BASE_ARRAY(x)
(((unsigned)(x) & 0x1FFF) << 0)
#define G_008F24_BASE_ARRAY(x) (((x) >>
0) & 0x1FFF)
#define C_008F24_BASE_ARRAY
0xFFFFE000
#define S_008F24_ARRAY_PITCH(x)
(((unsigned)(x) & 0x0F) << 13)
#define G_008F24_ARRAY_PITCH(x) (((x) >>
13) & 0x0F)
#define C_008F24_ARRAY_PITCH
0xFFFE1FFF
@@ -1561,41 +1561,41 @@
#define S_031108_CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD(x)
(((unsigned)(x) & 0x0F) << 0)
#define G_031108_CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD(x) (((x) >>
0) & 0x0F)
#define C_031108_CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD
0xFFFFFFF0
#define S_031108_CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD(x)
(((unsigned)(x) & 0x0F) << 4)
#define G_031108_CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD(x) (((x) >>
4) & 0x0F)
#define C_031108_CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD
0xFFFFFF0F
#define R_0098F8_GB_ADDR_CONFIG
0x0098F8
#define S_0098F8_NUM_PIPES(x)
(((unsigned)(x) & 0x07) << 0)
#define G_0098F8_NUM_PIPES(x) (((x) >>
0) & 0x07)
#define C_0098F8_NUM_PIPES
0xFFFFFFF8
-#define S_0098F8_PIPE_INTERLEAVE_SIZE(x)
(((unsigned)(x) & 0x07) << 3)
-#define G_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) >>
3) & 0x07)
-#define C_0098F8_PIPE_INTERLEAVE_SIZE
0xFFFFFFC7
+#define S_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(x)
(((unsigned)(x) & 0x07) << 3)
+#define G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(x) (((x) >>
3) & 0x07)
+#define C_0098F8_PIPE_INTERLEAVE_SIZE_GFX9
0xFFFFFFC7
#define S_0098F8_MAX_COMPRESSED_FRAGS(x)
(((unsigned)(x) & 0x03) << 6)
#define G_0098F8_MAX_COMPRESSED_FRAGS(x) (((x) >>
6) & 0x03)
#define C_0098F8_MAX_COMPRESSED_FRAGS
0xFFFFFF3F
#define S_0098F8_BANK_INTERLEAVE_SIZE(x)
(((unsigned)(x) & 0x07) << 8)
#define G_0098F8_BANK_INTERLEAVE_SIZE(x) (((x) >>
8) & 0x07)
#define C_0098F8_BANK_INTERLEAVE_SIZE
0xFFFFF8FF
#define S_0098F8_NUM_BANKS(x)
(((unsigned)(x) & 0x07) << 12)
#define G_0098F8_NUM_BANKS(x) (((x) >>
12) & 0x07)
#define C_0098F8_NUM_BANKS
0xFFFF8FFF
#define S_0098F8_SHADER_ENGINE_TILE_SIZE(x)
(((unsigned)(x) & 0x07) << 16)
#define G_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) >>
16) & 0x07)
#define C_0098F8_SHADER_ENGINE_TILE_SIZE
0xFFF8FFFF
-#define S_0098F8_NUM_SHADER_ENGINES(x)
(((unsigned)(x) & 0x03) << 19)
-#define G_0098F8_NUM_SHADER_ENGINES(x) (((x) >>
19) & 0x03)
-#define C_0098F8_NUM_SHADER_ENGINES
0xFFE7FFFF
-#define S_0098F8_NUM_GPUS(x)
(((unsigned)(x) & 0x07) << 21)
-#define G_0098F8_NUM_GPUS(x) (((x) >>
21) & 0x07)
-#define C_0098F8_NUM_GPUS
0xFF1FFFFF
+#define S_0098F8_NUM_SHADER_ENGINES_GFX9(x)
(((unsigned)(x) & 0x03) << 19)
+#define G_0098F8_NUM_SHADER_ENGINES_GFX9(x) (((x) >>
19) & 0x03)
+#define C_0098F8_NUM_SHADER_ENGINES_GFX9
0xFFE7FFFF
+#define S_0098F8_NUM_GPUS_GFX9(x)
(((unsigned)(x) & 0x07) << 21)
+#define G_0098F8_NUM_GPUS_GFX9(x) (((x) >>
21) & 0x07)
+#define C_0098F8_NUM_GPUS_GFX9
0xFF1FFFFF
#define S_0098F8_MULTI_GPU_TILE_SIZE(x)
(((unsigned)(x) & 0x03) << 24)
#define G_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) >>
24) & 0x03)
#define C_0098F8_MULTI_GPU_TILE_SIZE
0xFCFFFFFF
#define S_0098F8_NUM_RB_PER_SE(x)
(((unsigned)(x) & 0x03) << 26)
#define G_0098F8_NUM_RB_PER_SE(x) (((x) >>
26) & 0x03)
#define C_0098F8_NUM_RB_PER_SE
0xF3FFFFFF
#define S_0098F8_ROW_SIZE(x)
(((unsigned)(x) & 0x03) << 28)
#define G_0098F8_ROW_SIZE(x) (((x) >>
28) & 0x03)
#define C_0098F8_ROW_SIZE
0xCFFFFFFF
#define S_0098F8_NUM_LOWER_PIPES(x)
(((unsigned)(x) & 0x1) << 30)
@@ -4246,36 +4246,36 @@
#define C_028350_SC_MAP
0xFFFCFFFF
#define S_028350_SC_XSEL(x)
(((unsigned)(x) & 0x03) << 18)
#define G_028350_SC_XSEL(x) (((x) >>
18) & 0x03)
#define C_028350_SC_XSEL
0xFFF3FFFF
#define S_028350_SC_YSEL(x)
(((unsigned)(x) & 0x03) << 20)
#define G_028350_SC_YSEL(x) (((x) >>
20) & 0x03)
#define C_028350_SC_YSEL
0xFFCFFFFF
#define S_028350_SE_MAP(x)
(((unsigned)(x) & 0x03) << 24)
#define G_028350_SE_MAP(x) (((x) >>
24) & 0x03)
#define C_028350_SE_MAP
0xFCFFFFFF
-#define S_028350_SE_XSEL(x)
(((unsigned)(x) & 0x07) << 26)
-#define G_028350_SE_XSEL(x) (((x) >>
26) & 0x07)
-#define C_028350_SE_XSEL
0xE3FFFFFF
-#define S_028350_SE_YSEL(x)
(((unsigned)(x) & 0x07) << 29)
-#define G_028350_SE_YSEL(x) (((x) >>
29) & 0x07)
-#define C_028350_SE_YSEL
0x1FFFFFFF
+#define S_028350_SE_XSEL_GFX9(x)
(((unsigned)(x) & 0x07) << 26)
+#define G_028350_SE_XSEL_GFX9(x) (((x) >>
26) & 0x07)
+#define C_028350_SE_XSEL_GFX9
0xE3FFFFFF
+#define S_028350_SE_YSEL_GFX9(x)
(((unsigned)(x) & 0x07) << 29)
+#define G_028350_SE_YSEL_GFX9(x) (((x) >>
29) & 0x07)
+#define C_028350_SE_YSEL_GFX9
0x1FFFFFFF
#define R_028354_PA_SC_RASTER_CONFIG_1
0x028354
#define S_028354_SE_PAIR_MAP(x)
(((unsigned)(x) & 0x03) << 0)
#define G_028354_SE_PAIR_MAP(x) (((x) >>
0) & 0x03)
#define C_028354_SE_PAIR_MAP
0xFFFFFFFC
-#define S_028354_SE_PAIR_XSEL(x)
(((unsigned)(x) & 0x07) << 2)
-#define G_028354_SE_PAIR_XSEL(x) (((x) >>
2) & 0x07)
-#define C_028354_SE_PAIR_XSEL
0xFFFFFFE3
-#define S_028354_SE_PAIR_YSEL(x)
(((unsigned)(x) & 0x07) << 5)
-#define G_028354_SE_PAIR_YSEL(x) (((x) >>
5) & 0x07)
-#define C_028354_SE_PAIR_YSEL
0xFFFFFF1F
+#define S_028354_SE_PAIR_XSEL_GFX9(x)
(((unsigned)(x) & 0x07) << 2)
+#define G_028354_SE_PAIR_XSEL_GFX9(x) (((x) >>
2) & 0x07)
+#define C_028354_SE_PAIR_XSEL_GFX9
0xFFFFFFE3
+#define S_028354_SE_PAIR_YSEL_GFX9(x)
(((unsigned)(x) & 0x07) << 5)
+#define G_028354_SE_PAIR_YSEL_GFX9(x) (((x) >>
5) & 0x07)
+#define C_028354_SE_PAIR_YSEL_GFX9
0xFFFFFF1F
#define R_028358_PA_SC_SCREEN_EXTENT_CONTROL
0x028358
#define S_028358_SLICE_EVEN_ENABLE(x)
(((unsigned)(x) & 0x03) << 0)
#define G_028358_SLICE_EVEN_ENABLE(x) (((x) >>
0) & 0x03)
#define C_028358_SLICE_EVEN_ENABLE
0xFFFFFFFC
#define S_028358_SLICE_ODD_ENABLE(x)
(((unsigned)(x) & 0x03) << 2)
#define G_028358_SLICE_ODD_ENABLE(x) (((x) >>
2) & 0x03)
#define C_028358_SLICE_ODD_ENABLE
0xFFFFFFF3
#define R_02835C_PA_SC_TILE_STEERING_OVERRIDE
0x02835C
#define S_02835C_ENABLE(x)
(((unsigned)(x) & 0x1) << 0)
#define G_02835C_ENABLE(x) (((x) >>
0) & 0x1)
@@ -5137,23 +5137,23 @@
#define C_0287BC_EPITCH
0xFFFF0000
#define R_0287CC_CS_COPY_STATE
0x0287CC
#define S_0287CC_SRC_STATE_ID(x)
(((unsigned)(x) & 0x07) << 0)
#define G_0287CC_SRC_STATE_ID(x) (((x) >>
0) & 0x07)
#define C_0287CC_SRC_STATE_ID
0xFFFFFFF8
#define R_0287D4_PA_CL_POINT_X_RAD
0x0287D4
#define R_0287D8_PA_CL_POINT_Y_RAD
0x0287D8
#define R_0287DC_PA_CL_POINT_SIZE
0x0287DC
#define R_0287E0_PA_CL_POINT_CULL_RAD
0x0287E0
#define R_0287E4_VGT_DMA_BASE_HI
0x0287E4
-#define S_0287E4_BASE_ADDR(x)
(((unsigned)(x) & 0xFFFF) << 0)
-#define G_0287E4_BASE_ADDR(x) (((x) >>
0) & 0xFFFF)
-#define C_0287E4_BASE_ADDR
0xFFFF0000
+#define S_0287E4_BASE_ADDR_GFX9(x)
(((unsigned)(x) & 0xFFFF) << 0)
+#define G_0287E4_BASE_ADDR_GFX9(x) (((x) >>
0) & 0xFFFF)
+#define C_0287E4_BASE_ADDR_GFX9
0xFFFF0000
#define R_0287E8_VGT_DMA_BASE
0x0287E8
#define R_0287F0_VGT_DRAW_INITIATOR
0x0287F0
#define S_0287F0_SOURCE_SELECT(x)
(((unsigned)(x) & 0x03) << 0)
#define G_0287F0_SOURCE_SELECT(x) (((x) >>
0) & 0x03)
#define C_0287F0_SOURCE_SELECT
0xFFFFFFFC
#define S_0287F0_MAJOR_MODE(x)
(((unsigned)(x) & 0x03) << 2)
#define G_0287F0_MAJOR_MODE(x) (((x) >>
2) & 0x03)
#define C_0287F0_MAJOR_MODE
0xFFFFFFF3
#define S_0287F0_SPRITE_EN_R6XX(x)
(((unsigned)(x) & 0x1) << 4)
#define G_0287F0_SPRITE_EN_R6XX(x) (((x) >>
4) & 0x1)
@@ -6058,23 +6058,23 @@
#define C_028A84_DISABLE_RESET_ON_EOI
0xFFFFFFFD
#define S_028A84_NGG_DISABLE_PROVOK_REUSE(x)
(((unsigned)(x) & 0x1) << 2)
#define G_028A84_NGG_DISABLE_PROVOK_REUSE(x) (((x) >>
2) & 0x1)
#define C_028A84_NGG_DISABLE_PROVOK_REUSE
0xFFFFFFFB
#define R_028A88_VGT_DMA_NUM_INSTANCES
0x028A88
#define R_028A8C_VGT_PRIMITIVEID_RESET
0x028A8C
#define R_028A90_VGT_EVENT_INITIATOR
0x028A90
#define S_028A90_EVENT_TYPE(x)
(((unsigned)(x) & 0x3F) << 0)
#define G_028A90_EVENT_TYPE(x) (((x) >>
0) & 0x3F)
#define C_028A90_EVENT_TYPE
0xFFFFFFC0
-#define S_028A90_ADDRESS_HI(x)
(((unsigned)(x) & 0x1FFFF) << 10)
-#define G_028A90_ADDRESS_HI(x) (((x) >>
10) & 0x1FFFF)
-#define C_028A90_ADDRESS_HI
0xF80003FF
+#define S_028A90_ADDRESS_HI_GFX9(x)
(((unsigned)(x) & 0x1FFFF) << 10)
+#define G_028A90_ADDRESS_HI_GFX9(x) (((x) >>
10) & 0x1FFFF)
+#define C_028A90_ADDRESS_HI_GFX9
0xF80003FF
#define S_028A90_EXTENDED_EVENT(x)
(((unsigned)(x) & 0x1) << 27)
#define G_028A90_EXTENDED_EVENT(x) (((x) >>
27) & 0x1)
#define C_028A90_EXTENDED_EVENT
0xF7FFFFFF
#define R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
0x028A94
#define S_028A94_MAX_PRIMS_PER_SUBGROUP(x)
(((unsigned)(x) & 0xFFFF) << 0)
#define G_028A94_MAX_PRIMS_PER_SUBGROUP(x) (((x) >>
0) & 0xFFFF)
#define C_028A94_MAX_PRIMS_PER_SUBGROUP
0xFFFF0000
#define R_028A98_VGT_DRAW_PAYLOAD_CNTL
0x028A98
#define S_028A98_OBJPRIM_ID_EN(x)
(((unsigned)(x) & 0x1) << 0)
#define G_028A98_OBJPRIM_ID_EN(x) (((x) >>
0) & 0x1)
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index cb353d6..9145624 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -2254,23 +2254,23 @@
#define V_008F1C_SQ_RSRC_IMG_3D 0x0A
#define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B
#define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C
#define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D
#define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E
#define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F
#define R_008F20_SQ_IMG_RSRC_WORD4
0x008F20
#define S_008F20_DEPTH(x)
(((unsigned)(x) & 0x1FFF) << 0)
#define G_008F20_DEPTH(x) (((x) >>
0) & 0x1FFF)
#define C_008F20_DEPTH
0xFFFFE000
-#define S_008F20_PITCH(x)
(((unsigned)(x) & 0x3FFF) << 13)
-#define G_008F20_PITCH(x) (((x) >>
13) & 0x3FFF)
-#define C_008F20_PITCH
0xF8001FFF
+#define S_008F20_PITCH_GFX6(x)
(((unsigned)(x) & 0x3FFF) << 13)
+#define G_008F20_PITCH_GFX6(x) (((x) >>
13) & 0x3FFF)
+#define C_008F20_PITCH_GFX6
0xF8001FFF
#define R_008F24_SQ_IMG_RSRC_WORD5
0x008F24
#define S_008F24_BASE_ARRAY(x)
(((unsigned)(x) & 0x1FFF) << 0)
#define G_008F24_BASE_ARRAY(x) (((x) >>
0) & 0x1FFF)
#define C_008F24_BASE_ARRAY
0xFFFFE000
#define S_008F24_LAST_ARRAY(x)
(((unsigned)(x) & 0x1FFF) << 13)
#define G_008F24_LAST_ARRAY(x) (((x) >>
13) & 0x1FFF)
#define C_008F24_LAST_ARRAY
0xFC001FFF
#define R_008F28_SQ_IMG_RSRC_WORD6
0x008F28
#define S_008F28_MIN_LOD_WARN(x)
(((unsigned)(x) & 0xFFF) << 0)
#define G_008F28_MIN_LOD_WARN(x) (((x) >>
0) & 0xFFF)
@@ -2667,35 +2667,35 @@
#define S_009858_MSAA16_X(x)
(((unsigned)(x) & 0x03) << 16)
#define G_009858_MSAA16_X(x) (((x) >>
16) & 0x03)
#define C_009858_MSAA16_X
0xFFFCFFFF
#define S_009858_MSAA16_Y(x)
(((unsigned)(x) & 0x03) << 18)
#define G_009858_MSAA16_Y(x) (((x) >>
18) & 0x03)
#define C_009858_MSAA16_Y
0xFFF3FFFF
#define R_0098F8_GB_ADDR_CONFIG
0x0098F8
#define S_0098F8_NUM_PIPES(x)
(((unsigned)(x) & 0x07) << 0)
#define G_0098F8_NUM_PIPES(x) (((x) >>
0) & 0x07)
#define C_0098F8_NUM_PIPES
0xFFFFFFF8
-#define S_0098F8_PIPE_INTERLEAVE_SIZE(x)
(((unsigned)(x) & 0x07) << 4)
-#define G_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) >>
4) & 0x07)
-#define C_0098F8_PIPE_INTERLEAVE_SIZE
0xFFFFFF8F
+#define S_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(x)
(((unsigned)(x) & 0x07) << 4)
+#define G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(x) (((x) >>
4) & 0x07)
+#define C_0098F8_PIPE_INTERLEAVE_SIZE_GFX6
0xFFFFFF8F
#define S_0098F8_BANK_INTERLEAVE_SIZE(x)
(((unsigned)(x) & 0x07) << 8)
#define G_0098F8_BANK_INTERLEAVE_SIZE(x) (((x) >>
8) & 0x07)
#define C_0098F8_BANK_INTERLEAVE_SIZE
0xFFFFF8FF
-#define S_0098F8_NUM_SHADER_ENGINES(x)
(((unsigned)(x) & 0x03) << 12)
-#define G_0098F8_NUM_SHADER_ENGINES(x) (((x) >>
12) & 0x03)
-#define C_0098F8_NUM_SHADER_ENGINES
0xFFFFCFFF
+#define S_0098F8_NUM_SHADER_ENGINES_GFX6(x)
(((unsigned)(x) & 0x03) << 12)
+#define G_0098F8_NUM_SHADER_ENGINES_GFX6(x) (((x) >>
12) & 0x03)
+#define C_0098F8_NUM_SHADER_ENGINES_GFX6
0xFFFFCFFF
#define S_0098F8_SHADER_ENGINE_TILE_SIZE(x)
(((unsigned)(x) & 0x07) << 16)
#define G_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) >>
16) & 0x07)
#define C_0098F8_SHADER_ENGINE_TILE_SIZE
0xFFF8FFFF
-#define S_0098F8_NUM_GPUS(x)
(((unsigned)(x) & 0x07) << 20)
-#define G_0098F8_NUM_GPUS(x) (((x) >>
20) & 0x07)
-#define C_0098F8_NUM_GPUS
0xFF8FFFFF
+#define S_0098F8_NUM_GPUS_GFX6(x)
(((unsigned)(x) & 0x07) << 20)
+#define G_0098F8_NUM_GPUS_GFX6(x) (((x) >>
20) & 0x07)
+#define C_0098F8_NUM_GPUS_GFX6
0xFF8FFFFF
#define S_0098F8_MULTI_GPU_TILE_SIZE(x)
(((unsigned)(x) & 0x03) << 24)
#define G_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) >>
24) & 0x03)
#define C_0098F8_MULTI_GPU_TILE_SIZE
0xFCFFFFFF
#define S_0098F8_ROW_SIZE(x)
(((unsigned)(x) & 0x03) << 28)
#define G_0098F8_ROW_SIZE(x) (((x) >>
28) & 0x03)
#define C_0098F8_ROW_SIZE
0xCFFFFFFF
#define S_0098F8_NUM_LOWER_PIPES(x)
(((unsigned)(x) & 0x1) << 30)
#define G_0098F8_NUM_LOWER_PIPES(x) (((x) >>
30) & 0x1)
#define C_0098F8_NUM_LOWER_PIPES
0xBFFFFFFF
#define R_009910_GB_TILE_MODE0
0x009910
@@ -5507,53 +5507,53 @@
#define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01
#define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02
#define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03
#define S_028350_SE_MAP(x)
(((unsigned)(x) & 0x03) << 24)
#define G_028350_SE_MAP(x) (((x) >>
24) & 0x03)
#define C_028350_SE_MAP
0xFCFFFFFF
#define V_028350_RASTER_CONFIG_SE_MAP_0 0x00
#define V_028350_RASTER_CONFIG_SE_MAP_1 0x01
#define V_028350_RASTER_CONFIG_SE_MAP_2 0x02
#define V_028350_RASTER_CONFIG_SE_MAP_3 0x03
-#define S_028350_SE_XSEL(x)
(((unsigned)(x) & 0x03) << 26)
-#define G_028350_SE_XSEL(x) (((x) >>
26) & 0x03)
-#define C_028350_SE_XSEL
0xF3FFFFFF
+#define S_028350_SE_XSEL_GFX6(x)
(((unsigned)(x) & 0x03) << 26)
+#define G_028350_SE_XSEL_GFX6(x) (((x) >>
26) & 0x03)
+#define C_028350_SE_XSEL_GFX6
0xF3FFFFFF
#define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00
#define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01
#define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02
#define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03
-#define S_028350_SE_YSEL(x)
(((unsigned)(x) & 0x03) << 28)
-#define G_028350_SE_YSEL(x) (((x) >>
28) & 0x03)
-#define C_028350_SE_YSEL
0xCFFFFFFF
+#define S_028350_SE_YSEL_GFX6(x)
(((unsigned)(x) & 0x03) << 28)
+#define G_028350_SE_YSEL_GFX6(x) (((x) >>
28) & 0x03)
+#define C_028350_SE_YSEL_GFX6
0xCFFFFFFF
#define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00
#define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01
#define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02
#define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03
/* CIK */
#define R_028354_PA_SC_RASTER_CONFIG_1
0x028354
#define S_028354_SE_PAIR_MAP(x)
(((unsigned)(x) & 0x03) << 0)
#define G_028354_SE_PAIR_MAP(x) (((x) >>
0) & 0x03)
#define C_028354_SE_PAIR_MAP
0xFFFFFFFC
#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_0 0x00
#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_1 0x01
#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_2 0x02
#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_3 0x03
-#define S_028354_SE_PAIR_XSEL(x)
(((unsigned)(x) & 0x03) << 2)
-#define G_028354_SE_PAIR_XSEL(x) (((x) >>
2) & 0x03)
-#define C_028354_SE_PAIR_XSEL
0xFFFFFFF3
+#define S_028354_SE_PAIR_XSEL_GFX6(x)
(((unsigned)(x) & 0x03) << 2)
+#define G_028354_SE_PAIR_XSEL_GFX6(x) (((x) >>
2) & 0x03)
+#define C_028354_SE_PAIR_XSEL_GFX6
0xFFFFFFF3
#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE 0x00
#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE 0x01
#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE 0x02
#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE 0x03
-#define S_028354_SE_PAIR_YSEL(x)
(((unsigned)(x) & 0x03) << 4)
-#define G_028354_SE_PAIR_YSEL(x) (((x) >>
4) & 0x03)
-#define C_028354_SE_PAIR_YSEL
0xFFFFFFCF
+#define S_028354_SE_PAIR_YSEL_GFX6(x)
(((unsigned)(x) & 0x03) << 4)
+#define G_028354_SE_PAIR_YSEL_GFX6(x) (((x) >>
4) & 0x03)
+#define C_028354_SE_PAIR_YSEL_GFX6
0xFFFFFFCF
#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE 0x00
#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE 0x01
#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE 0x02
#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE 0x03
#define R_028358_PA_SC_SCREEN_EXTENT_CONTROL
0x028358
#define S_028358_SLICE_EVEN_ENABLE(x)
(((unsigned)(x) & 0x03) << 0)
#define G_028358_SLICE_EVEN_ENABLE(x) (((x) >>
0) & 0x03)
#define C_028358_SLICE_EVEN_ENABLE
0xFFFFFFFC
#define S_028358_SLICE_ODD_ENABLE(x)
(((unsigned)(x) & 0x03) << 2)
#define G_028358_SLICE_ODD_ENABLE(x) (((x) >>
2) & 0x03)
@@ -6697,23 +6697,23 @@
#define R_02879C_CB_BLEND7_CONTROL
0x02879C
#define R_0287CC_CS_COPY_STATE
0x0287CC
#define S_0287CC_SRC_STATE_ID(x)
(((unsigned)(x) & 0x07) << 0)
#define G_0287CC_SRC_STATE_ID(x) (((x) >>
0) & 0x07)
#define C_0287CC_SRC_STATE_ID
0xFFFFFFF8
#define R_0287D4_PA_CL_POINT_X_RAD
0x0287D4
#define R_0287D8_PA_CL_POINT_Y_RAD
0x0287D8
#define R_0287DC_PA_CL_POINT_SIZE
0x0287DC
#define R_0287E0_PA_CL_POINT_CULL_RAD
0x0287E0
#define R_0287E4_VGT_DMA_BASE_HI
0x0287E4
-#define S_0287E4_BASE_ADDR(x)
(((unsigned)(x) & 0xFF) << 0)
-#define G_0287E4_BASE_ADDR(x) (((x) >>
0) & 0xFF)
-#define C_0287E4_BASE_ADDR
0xFFFFFF00
+#define S_0287E4_BASE_ADDR_GFX6(x)
(((unsigned)(x) & 0xFF) << 0)
+#define G_0287E4_BASE_ADDR_GFX6(x) (((x) >>
0) & 0xFF)
+#define C_0287E4_BASE_ADDR_GFX6
0xFFFFFF00
#define R_0287E8_VGT_DMA_BASE
0x0287E8
#define R_0287F0_VGT_DRAW_INITIATOR
0x0287F0
#define S_0287F0_SOURCE_SELECT(x)
(((unsigned)(x) & 0x03) << 0)
#define G_0287F0_SOURCE_SELECT(x) (((x) >>
0) & 0x03)
#define C_0287F0_SOURCE_SELECT
0xFFFFFFFC
#define V_0287F0_DI_SRC_SEL_DMA 0x00
#define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01 /*
not on CIK */
#define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02
#define V_0287F0_DI_SRC_SEL_RESERVED 0x03
#define S_0287F0_MAJOR_MODE(x)
(((unsigned)(x) & 0x03) << 2)
@@ -7816,23 +7816,23 @@
#define V_028A90_THREAD_TRACE_START 0x33
#define V_028A90_THREAD_TRACE_STOP 0x34
#define V_028A90_THREAD_TRACE_MARKER 0x35
#define V_028A90_THREAD_TRACE_FLUSH 0x36
#define V_028A90_THREAD_TRACE_FINISH 0x37
/* CIK */
#define V_028A90_PIXEL_PIPE_STAT_CONTROL 0x38
#define V_028A90_PIXEL_PIPE_STAT_DUMP 0x39
#define V_028A90_PIXEL_PIPE_STAT_RESET 0x3A
/* */
-#define S_028A90_ADDRESS_HI(x)
(((unsigned)(x) & 0x1FF) << 18)
-#define G_028A90_ADDRESS_HI(x) (((x) >>
18) & 0x1FF)
-#define C_028A90_ADDRESS_HI
0xF803FFFF
+#define S_028A90_ADDRESS_HI_GFX6(x)
(((unsigned)(x) & 0x1FF) << 18)
+#define G_028A90_ADDRESS_HI_GFX6(x) (((x) >>
18) & 0x1FF)
+#define C_028A90_ADDRESS_HI_GFX6
0xF803FFFF
#define S_028A90_EXTENDED_EVENT(x)
(((unsigned)(x) & 0x1) << 27)
#define G_028A90_EXTENDED_EVENT(x) (((x) >>
27) & 0x1)
#define C_028A90_EXTENDED_EVENT
0xF7FFFFFF
#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
0x028A94
#define S_028A94_RESET_EN(x)
(((unsigned)(x) & 0x1) << 0)
#define G_028A94_RESET_EN(x) (((x) >>
0) & 0x1)
#define C_028A94_RESET_EN
0xFFFFFFFE
#define R_028AA0_VGT_INSTANCE_STEP_RATE_0
0x028AA0
#define R_028AA4_VGT_INSTANCE_STEP_RATE_1
0x028AA4
#define R_028AA8_IA_MULTI_VGT_PARAM
0x028AA8
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 2e62725..c13bc94 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -387,28 +387,28 @@ void si_set_mutable_tex_desc_fields(struct r600_texture
*tex,
if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
tex = tex->flushed_depth_texture;
is_stencil = false;
}
va = tex->resource.gpu_address + base_level_info->offset;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[3] &= C_008F1C_TILING_INDEX;
- state[4] &= C_008F20_PITCH;
+ state[4] &= C_008F20_PITCH_GFX6;
state[6] &= C_008F28_COMPRESSION_EN;
state[0] = va >> 8;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
is_stencil));
- state[4] |= S_008F20_PITCH(pitch - 1);
+ state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
if (tex->dcc_offset && first_level < tex->surface.num_dcc_levels) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = ((!tex->dcc_separate_buffer ?
tex->resource.gpu_address : 0) +
tex->dcc_offset +
base_level_info->dcc_offset) >> 8;
} else if (tex->tc_compatible_htile) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = tex->htile_buffer->gpu_address >> 8;
}
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index a56da79..efe1f41 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2993,21 +2993,21 @@ si_make_texture_descriptor(struct si_screen *screen,
S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
fmask_state[2] = S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1);
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
S_008F1C_TYPE(si_tex_dim(res->target, target,
0));
fmask_state[4] = S_008F20_DEPTH(depth - 1) |
- S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
+ S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels
- 1);
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
S_008F24_LAST_ARRAY(last_layer);
fmask_state[6] = 0;
fmask_state[7] = 0;
}
}
/**
* Create a sampler view.
*
--
2.7.4
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