From: Dave Airlie <airl...@redhat.com>
If we had no rasterization, we'd emit SPI color
format as all 0's the hw dislikes this, add the workaround
from radeonsi.
Found while debugging tessellation
v2: handle at pipeline stage, we have to handle
it after we process the fragment shader. (Bas)
Signed-off-by: Dave Airlie <airl...@redhat.com>
---
src/amd/vulkan/radv_pipeline.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 094d636..e353a96 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1602,6 +1602,27 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
pipeline->graphics.prim_restart_enable =
!!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
/* prim vertex count will need TESS changes */
pipeline->graphics.prim_vertex_count =
prim_size_table[pipeline->graphics.prim];
+
+ /* Ensure that some export memory is always allocated, for two reasons:
+ *
+ * 1) Correctness: The hardware ignores the EXEC mask if no export
+ * memory is allocated, so KILL and alpha test do not work correctly
+ * without this.
+ * 2) Performance: Every shader needs at least a NULL export, even when
+ * it writes no color/depth output. The NULL export instruction
+ * stalls without this setting.
+ *
+ * Don't add this to CB_SHADER_MASK.
+ */
+ if (!pCreateInfo->pColorBlendState) {
+ unsigned spi_shader_col_format =
pipeline->graphics.blend.spi_shader_col_format;
+ struct radv_shader_variant *ps =
pipeline->shaders[MESA_SHADER_FRAGMENT];
+ if (!spi_shader_col_format &&
+ !ps->info.fs.writes_z &&
+ !ps->info.fs.writes_stencil &&
+ !ps->info.fs.writes_sample_mask)
+ pipeline->graphics.blend.spi_shader_col_format =
V_028714_SPI_SHADER_32_R;
+ }
const VkPipelineVertexInputStateCreateInfo *vi_info =
pCreateInfo->pVertexInputState;
--
2.9.3
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