From: Marek Olšák <[email protected]>
Most things are in place. Ideally we won't see decompress blits for stencil
anymore.
---
src/gallium/drivers/radeonsi/si_blit.c | 2 ++
src/gallium/drivers/radeonsi/si_descriptors.c | 8 ++++----
src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 448533d..59334db 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -337,20 +337,22 @@ si_flush_depth_texture(struct si_context *sctx,
if (levels_s) {
if (r600_can_sample_zs(tex, true))
inplace_planes |= PIPE_MASK_S;
else
copy_planes |= PIPE_MASK_S;
}
}
assert(!tex->tc_compatible_htile || levels_z == 0);
+ assert(!tex->tc_compatible_htile || levels_s == 0 ||
+ !r600_can_sample_zs(tex, true));
/* We may have to allocate the flushed texture here when called from
* si_decompress_subresource.
*/
if (copy_planes &&
(tex->flushed_depth_texture ||
r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b,
NULL))) {
struct r600_texture *dst = tex->flushed_depth_texture;
unsigned fully_copied_levels;
unsigned levels = 0;
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 61eb2f1..7a2b71d 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -332,22 +332,21 @@ static void si_sampler_view_add_buffer(struct si_context
*sctx,
/* Now add separate DCC or HTILE. */
rtex = (struct r600_texture*)resource;
if (rtex->dcc_separate_buffer) {
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rtex->dcc_separate_buffer,
usage,
RADEON_PRIO_DCC, check_mem);
}
if (rtex->htile_buffer &&
- rtex->tc_compatible_htile &&
- !is_stencil_sampler) {
+ rtex->tc_compatible_htile) {
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rtex->htile_buffer, usage,
RADEON_PRIO_HTILE,
check_mem);
}
}
static void si_sampler_views_begin_new_cs(struct si_context *sctx,
struct si_sampler_views *views)
{
unsigned mask = views->enabled_mask;
@@ -417,21 +416,21 @@ void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen,
if (sscreen->b.chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
if (vi_dcc_enabled(tex, first_level)) {
meta_va = (!tex->dcc_separate_buffer ?
tex->resource.gpu_address : 0) +
tex->dcc_offset;
if (sscreen->b.chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if (tex->tc_compatible_htile && !is_stencil) {
+ } else if (tex->tc_compatible_htile) {
meta_va = tex->htile_buffer->gpu_address;
}
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
}
}
if (sscreen->b.chip_class >= GFX9) {
@@ -564,21 +563,22 @@ static bool is_compressed_colortex(struct r600_texture
*rtex)
{
return rtex->fmask.size ||
(rtex->dirty_level_mask &&
(rtex->cmask.size || rtex->dcc_offset));
}
static bool depth_needs_decompression(struct r600_texture *rtex,
struct si_sampler_view *sview)
{
return rtex->db_compatible &&
- (!rtex->tc_compatible_htile || sview->is_stencil_sampler);
+ (!rtex->tc_compatible_htile ||
+ !r600_can_sample_zs(rtex, sview->is_stencil_sampler));
}
static void si_update_compressed_tex_shader_mask(struct si_context *sctx,
unsigned shader)
{
struct si_textures_info *samplers = &sctx->samplers[shader];
unsigned shader_bit = 1 << shader;
if (samplers->depth_texture_mask ||
samplers->compressed_colortex_mask ||
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 77df643..cd069e3 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1391,21 +1391,22 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
if (sctx->framebuffer.do_update_surf_dirtiness) {
/* Set the depth buffer as dirty. */
if (sctx->framebuffer.state.zsbuf) {
struct pipe_surface *surf =
sctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture
*)surf->texture;
if (!rtex->tc_compatible_htile)
rtex->dirty_level_mask |= 1 <<
surf->u.tex.level;
- if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER &&
+ (!rtex->tc_compatible_htile || !rtex->can_sample_s))
rtex->stencil_dirty_level_mask |= 1 <<
surf->u.tex.level;
}
if (sctx->framebuffer.compressed_cb_mask) {
struct pipe_surface *surf;
struct r600_texture *rtex;
unsigned mask = sctx->framebuffer.compressed_cb_mask;
do {
unsigned i = u_bit_scan(&mask);
surf = sctx->framebuffer.state.cbufs[i];
--
2.7.4
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