Marek Olšák wrote:
From: Marek Olšák <marek.ol...@amd.com>
The kernel sort of does the same thing with fences.
v2: do emit partial flushes on SI
Bugzilla seems to be down currently so replying here.
On R9 285 with current agd5f 4.13-wip kernel I get some slight
artifacts on Unigine Valley since this.
Valley is run 1920x1080 full screen everything on/highest settings.
Artifacts start scene 2 with rare brief flashes of blue chequered patches.
---
src/gallium/drivers/radeonsi/si_hw_context.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 345825a..76b295f 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -122,27 +122,31 @@ void si_context_gfx_flush(void *context, unsigned flags,
}
ctx->gfx_flush_in_progress = true;
/* This CE dump should be done in parallel with the last draw. */
if (ctx->ce_ib)
si_ce_save_all_descriptors_at_ib_end(ctx);
r600_preflush_suspend_features(&ctx->b);
- ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
- SI_CONTEXT_PS_PARTIAL_FLUSH;
-
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
- if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
- ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
+ if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) {
+ ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+ SI_CONTEXT_CS_PARTIAL_FLUSH |
+ SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1;
+ } else if (ctx->b.chip_class == SI) {
+ /* The kernel doesn't wait for idle before doing SURFACE_SYNC.
*/
+ ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+ SI_CONTEXT_CS_PARTIAL_FLUSH;
+ }
si_emit_cache_flush(ctx);
if (ctx->trace_buf)
si_trace_emit(ctx);
if (ctx->is_debug) {
/* Save the IB for debug contexts. */
radeon_clear_saved_cs(&ctx->last_gfx);
radeon_save_cs(ws, cs, &ctx->last_gfx);
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