Yes please!
I find this much more intuitive, as a bonus =)
Reviewed-by: Thomas Helland <thomashellan...@gmail.com>
2017-07-08 2:36 GMT+02:00 Marek Olšák <mar...@gmail.com>:
> From: Marek Olšák <marek.ol...@amd.com>
>
> It can't parse "llu".
> ---
> src/gallium/drivers/r600/r600_state_common.c | 4 +--
> src/gallium/drivers/radeon/r600_pipe_common.h | 44
> ++++++++++++-------------
> src/gallium/drivers/radeonsi/si_debug.c | 4 +--
> src/gallium/drivers/radeonsi/si_shader.c | 2 +-
> src/gallium/drivers/radeonsi/si_state_shaders.c | 10 +++---
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 +-
> src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 +-
> src/mesa/state_tracker/st_atom.h | 4 +--
> 8 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_state_common.c
> b/src/gallium/drivers/r600/r600_state_common.c
> index 8ace779..4c97efa 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -840,25 +840,25 @@ static void *r600_create_shader_state(struct
> pipe_context *ctx,
>
> for (i = 0; i < sel->info.num_outputs; i++) {
> unsigned name = sel->info.output_semantic_name[i];
> unsigned index = sel->info.output_semantic_index[i];
>
> switch (name) {
> case TGSI_SEMANTIC_TESSINNER:
> case TGSI_SEMANTIC_TESSOUTER:
> case TGSI_SEMANTIC_PATCH:
> sel->lds_patch_outputs_written_mask |=
> - 1llu <<
> r600_get_lds_unique_index(name, index);
> + 1ull <<
> r600_get_lds_unique_index(name, index);
> break;
> default:
> sel->lds_outputs_written_mask |=
> - 1llu <<
> r600_get_lds_unique_index(name, index);
> + 1ull <<
> r600_get_lds_unique_index(name, index);
> }
> }
> break;
> default:
> break;
> }
>
> return sel;
> }
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index b22a3a7..5c761f3 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -83,42 +83,42 @@
> #define DBG_NO_TGSI (1 << 13)
> #define DBG_NO_ASM (1 << 14)
> #define DBG_PREOPT_IR (1 << 15)
> #define DBG_CHECK_IR (1 << 16)
> #define DBG_NO_OPT_VARIANT (1 << 17)
> #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
> /* gaps */
> #define DBG_TEST_DMA (1 << 20)
> /* Bits 21-31 are reserved for the r600g driver. */
> /* features */
> -#define DBG_NO_ASYNC_DMA (1llu << 32)
> -#define DBG_NO_HYPERZ (1llu << 33)
> -#define DBG_NO_DISCARD_RANGE (1llu << 34)
> -#define DBG_NO_2D_TILING (1llu << 35)
> -#define DBG_NO_TILING (1llu << 36)
> -#define DBG_SWITCH_ON_EOP (1llu << 37)
> -#define DBG_FORCE_DMA (1llu << 38)
> -#define DBG_PRECOMPILE (1llu << 39)
> -#define DBG_INFO (1llu << 40)
> -#define DBG_NO_WC (1llu << 41)
> -#define DBG_CHECK_VM (1llu << 42)
> -#define DBG_NO_DCC (1llu << 43)
> -#define DBG_NO_DCC_CLEAR (1llu << 44)
> -#define DBG_NO_RB_PLUS (1llu << 45)
> -#define DBG_SI_SCHED (1llu << 46)
> -#define DBG_MONOLITHIC_SHADERS (1llu << 47)
> -#define DBG_NO_CE (1llu << 48)
> -#define DBG_UNSAFE_MATH (1llu << 49)
> -#define DBG_NO_DCC_FB (1llu << 50)
> -#define DBG_TEST_VMFAULT_CP (1llu << 51)
> -#define DBG_TEST_VMFAULT_SDMA (1llu << 52)
> -#define DBG_TEST_VMFAULT_SHADER (1llu << 53)
> +#define DBG_NO_ASYNC_DMA (1ull << 32)
> +#define DBG_NO_HYPERZ (1ull << 33)
> +#define DBG_NO_DISCARD_RANGE (1ull << 34)
> +#define DBG_NO_2D_TILING (1ull << 35)
> +#define DBG_NO_TILING (1ull << 36)
> +#define DBG_SWITCH_ON_EOP (1ull << 37)
> +#define DBG_FORCE_DMA (1ull << 38)
> +#define DBG_PRECOMPILE (1ull << 39)
> +#define DBG_INFO (1ull << 40)
> +#define DBG_NO_WC (1ull << 41)
> +#define DBG_CHECK_VM (1ull << 42)
> +#define DBG_NO_DCC (1ull << 43)
> +#define DBG_NO_DCC_CLEAR (1ull << 44)
> +#define DBG_NO_RB_PLUS (1ull << 45)
> +#define DBG_SI_SCHED (1ull << 46)
> +#define DBG_MONOLITHIC_SHADERS (1ull << 47)
> +#define DBG_NO_CE (1ull << 48)
> +#define DBG_UNSAFE_MATH (1ull << 49)
> +#define DBG_NO_DCC_FB (1ull << 50)
> +#define DBG_TEST_VMFAULT_CP (1ull << 51)
> +#define DBG_TEST_VMFAULT_SDMA (1ull << 52)
> +#define DBG_TEST_VMFAULT_SHADER (1ull << 53)
>
> #define R600_MAP_BUFFER_ALIGNMENT 64
> #define R600_MAX_VIEWPORTS 16
>
> #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
>
> enum r600_coherency {
> R600_COHERENCY_NONE, /* no cache flushes needed */
> R600_COHERENCY_SHADER,
> R600_COHERENCY_CB_META,
> diff --git a/src/gallium/drivers/radeonsi/si_debug.c
> b/src/gallium/drivers/radeonsi/si_debug.c
> index 35bfec7..0d26ce5 100644
> --- a/src/gallium/drivers/radeonsi/si_debug.c
> +++ b/src/gallium/drivers/radeonsi/si_debug.c
> @@ -337,21 +337,21 @@ static void si_dump_bo_list(struct si_context *sctx,
> (va - previous_va_end) / page_size);
> }
> }
>
> /* Print the buffer. */
> fprintf(f, " %10"PRIu64" 0x%013"PRIX64"
> 0x%013"PRIX64" ",
> size / page_size, va / page_size, (va + size) /
> page_size);
>
> /* Print the usage. */
> for (j = 0; j < 64; j++) {
> - if (!(saved->bo_list[i].priority_usage & (1llu << j)))
> + if (!(saved->bo_list[i].priority_usage & (1ull << j)))
> continue;
>
> fprintf(f, "%s%s", !hit ? "" : ", ",
> priority_to_string(j));
> hit = true;
> }
> fprintf(f, "\n");
> }
> fprintf(f, "\nNote: The holes represent memory not used by the IB.\n"
> " Other buffers can still be allocated there.\n\n");
> }
> @@ -887,21 +887,21 @@ static bool si_vm_fault_occured(struct si_context
> *sctx, uint32_t *out_addr)
> /* Get the timestamp. */
> if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
> static bool hit = false;
> if (!hit) {
> fprintf(stderr, "%s: failed to parse line
> '%s'\n",
> __func__, line);
> hit = true;
> }
> continue;
> }
> - timestamp = sec * 1000000llu + usec;
> + timestamp = sec * 1000000ull + usec;
>
> /* If just updating the timestamp. */
> if (!out_addr)
> continue;
>
> /* Process messages only if the timestamp is newer. */
> if (timestamp <= sctx->dmesg_timestamp)
> continue;
>
> /* Only process the first VM fault. */
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 55d1232..349e57b 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -7131,21 +7131,21 @@ static void si_build_ps_epilog_function(struct
> si_shader_context *ctx,
> /* Find the last color export. */
> if (!key->ps_epilog.writes_z &&
> !key->ps_epilog.writes_stencil &&
> !key->ps_epilog.writes_samplemask) {
> unsigned spi_format =
> key->ps_epilog.states.spi_shader_col_format;
>
> /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
> if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf
> > 0) {
> /* Just set this if any of the colorbuffers are
> enabled. */
> if (spi_format &
> - ((1llu << (4 * (key->ps_epilog.states.last_cbuf +
> 1))) - 1))
> + ((1ull << (4 * (key->ps_epilog.states.last_cbuf +
> 1))) - 1))
> last_color_export = 0;
> } else {
> for (i = 0; i < 8; i++)
> if (colors_written & (1 << i) &&
> (spi_format >> (i * 4)) & 0xf)
> last_color_export = i;
> }
> }
>
> while (colors_written) {
> diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
> b/src/gallium/drivers/radeonsi/si_state_shaders.c
> index af3f2a9..f1170be 100644
> --- a/src/gallium/drivers/radeonsi/si_state_shaders.c
> +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
> @@ -2028,45 +2028,45 @@ static void *si_create_shader_selector(struct
> pipe_context *ctx,
> sel->max_gs_stream = MAX2(sel->max_gs_stream,
> sel->so.output[i].stream);
>
> sel->gs_input_verts_per_prim =
>
> u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
> break;
>
> case PIPE_SHADER_TESS_CTRL:
> /* Always reserve space for these. */
> sel->patch_outputs_written |=
> - (1llu <<
> si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
> - (1llu <<
> si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
> + (1ull <<
> si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
> + (1ull <<
> si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
> /* fall through */
> case PIPE_SHADER_VERTEX:
> case PIPE_SHADER_TESS_EVAL:
> for (i = 0; i < sel->info.num_outputs; i++) {
> unsigned name = sel->info.output_semantic_name[i];
> unsigned index = sel->info.output_semantic_index[i];
>
> switch (name) {
> case TGSI_SEMANTIC_TESSINNER:
> case TGSI_SEMANTIC_TESSOUTER:
> case TGSI_SEMANTIC_PATCH:
> sel->patch_outputs_written |=
> - 1llu <<
> si_shader_io_get_unique_index_patch(name, index);
> + 1ull <<
> si_shader_io_get_unique_index_patch(name, index);
> break;
>
> case TGSI_SEMANTIC_GENERIC:
> /* don't process indices the function can't
> handle */
> if (index >= SI_MAX_IO_GENERIC)
> break;
> /* fall through */
> default:
> sel->outputs_written |=
> - 1llu <<
> si_shader_io_get_unique_index(name, index);
> + 1ull <<
> si_shader_io_get_unique_index(name, index);
> break;
> case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
> case TGSI_SEMANTIC_EDGEFLAG:
> break;
> }
> }
> sel->esgs_itemsize = util_last_bit64(sel->outputs_written) *
> 16;
>
> /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
> * conflicts, i.e. each vertex will start at a different bank.
> @@ -2081,21 +2081,21 @@ static void *si_create_shader_selector(struct
> pipe_context *ctx,
> unsigned index = sel->info.input_semantic_index[i];
>
> switch (name) {
> case TGSI_SEMANTIC_GENERIC:
> /* don't process indices the function can't
> handle */
> if (index >= SI_MAX_IO_GENERIC)
> break;
> /* fall through */
> default:
> sel->inputs_read |=
> - 1llu <<
> si_shader_io_get_unique_index(name, index);
> + 1ull <<
> si_shader_io_get_unique_index(name, index);
> break;
> case TGSI_SEMANTIC_PCOORD: /* ignore this */
> break;
> }
> }
>
> for (i = 0; i < 8; i++)
> if (sel->info.colors_written & (1 << i))
> sel->colors_written_4bit |= 0xf << (4 * i);
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index a1fb045..d266253 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -529,21 +529,21 @@ static unsigned amdgpu_cs_add_buffer(struct
> radeon_winsys_cs *rcs,
>
> buffer = &cs->real_buffers[index];
> } else {
> index = amdgpu_lookup_or_add_sparse_buffer(acs, bo);
> if (index < 0)
> return 0;
>
> buffer = &cs->sparse_buffers[index];
> }
>
> - buffer->u.real.priority_usage |= 1llu << priority;
> + buffer->u.real.priority_usage |= 1ull << priority;
> buffer->usage |= usage;
>
> cs->last_added_bo = bo;
> cs->last_added_bo_index = index;
> cs->last_added_bo_usage = buffer->usage;
> cs->last_added_bo_priority_usage = buffer->u.real.priority_usage;
> return index;
> }
>
> static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib
> *ib)
> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
> b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
> index 5246053..1e7060e 100644
> --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
> @@ -360,21 +360,21 @@ static unsigned radeon_drm_cs_add_buffer(struct
> radeon_winsys_cs *rcs,
> index = cs->csc->slab_buffers[index].u.slab.real_idx;
> } else {
> index = radeon_lookup_or_add_real_buffer(cs, bo);
> }
>
> reloc = &cs->csc->relocs[index];
> added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
> reloc->read_domains |= rd;
> reloc->write_domain |= wd;
> reloc->flags = MAX2(reloc->flags, priority);
> - cs->csc->relocs_bo[index].u.real.priority_usage |= 1llu << priority;
> + cs->csc->relocs_bo[index].u.real.priority_usage |= 1ull << priority;
>
> if (added_domains & RADEON_DOMAIN_VRAM)
> cs->base.used_vram += bo->base.size;
> else if (added_domains & RADEON_DOMAIN_GTT)
> cs->base.used_gart += bo->base.size;
>
> return index;
> }
>
> static int radeon_drm_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
> diff --git a/src/mesa/state_tracker/st_atom.h
> b/src/mesa/state_tracker/st_atom.h
> index 663bc06..f9711d5 100644
> --- a/src/mesa/state_tracker/st_atom.h
> +++ b/src/mesa/state_tracker/st_atom.h
> @@ -61,21 +61,21 @@ st_pipe_vertex_format(GLenum type, GLuint size, GLenum
> format,
> /* Define ST_NEW_xxx_INDEX */
> enum {
> #define ST_STATE(FLAG, st_update) FLAG##_INDEX,
> #include "st_atom_list.h"
> #undef ST_STATE
> };
>
> /* Define ST_NEW_xxx values as static const uint64_t values.
> * We can't use an enum type because MSVC doesn't allow 64-bit enum values.
> */
> -#define ST_STATE(FLAG, st_update) static const uint64_t FLAG = 1llu <<
> FLAG##_INDEX;
> +#define ST_STATE(FLAG, st_update) static const uint64_t FLAG = 1ull <<
> FLAG##_INDEX;
> #include "st_atom_list.h"
> #undef ST_STATE
>
> /* Declare function prototypes. */
> #define ST_STATE(FLAG, st_update) void st_update(struct st_context *st);
> #include "st_atom_list.h"
> #undef ST_STATE
>
> /* Combined state flags. */
> #define ST_NEW_SAMPLERS (ST_NEW_VS_SAMPLERS | \
> @@ -138,21 +138,21 @@ enum {
> #define ST_ALL_SHADER_RESOURCES (ST_NEW_SAMPLER_VIEWS | \
> ST_NEW_SAMPLERS | \
> ST_NEW_CONSTANTS | \
> ST_NEW_UNIFORM_BUFFER | \
> ST_NEW_ATOMIC_BUFFER | \
> ST_NEW_STORAGE_BUFFER | \
> ST_NEW_IMAGE_UNITS)
>
> /* All state flags within each group: */
> #define ST_PIPELINE_RENDER_STATE_MASK (ST_NEW_CS_STATE - 1)
> -#define ST_PIPELINE_COMPUTE_STATE_MASK (0xffllu << ST_NEW_CS_STATE_INDEX)
> +#define ST_PIPELINE_COMPUTE_STATE_MASK (0xffull << ST_NEW_CS_STATE_INDEX)
> #define ST_PIPELINE_CLEAR_STATE_MASK (ST_NEW_FB_STATE | \
> ST_NEW_SCISSOR | \
> ST_NEW_WINDOW_RECTANGLES)
> /* For ReadPixels, ReadBuffer, GetSamplePosition: */
> #define ST_PIPELINE_UPDATE_FB_STATE_MASK (ST_NEW_FB_STATE)
>
> #define ST_ALL_STATES_MASK (ST_PIPELINE_RENDER_STATE_MASK | \
> ST_PIPELINE_COMPUTE_STATE_MASK)
>
> #endif
> --
> 2.7.4
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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