We need this split for the same reason that we need the split for CCS:
intel_miptree_supports_hiz is called *before* we choose the actual
tiling. Adding a tiling_supports_hiz helper lets choose_aux_usage
more accurately decide whether or not to enable hiz. In particular,
this prevents us from enabling HiZ on linear depth buffers.
Cc: Topi Pohjolainen <topi.pohjolai...@gmail.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 12b8d04..0fc9b67 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -213,6 +213,15 @@ intel_miptree_supports_ccs(struct brw_context *brw,
}
static bool
+intel_tiling_supports_hiz(const struct brw_context *brw, unsigned tiling)
+{
+ if (brw->gen < 6)
+ return false;
+
+ return tiling == I915_TILING_Y;
+}
+
+static bool
intel_miptree_supports_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
@@ -597,7 +606,8 @@ intel_miptree_choose_aux_usage(struct brw_context *brw,
} else {
mt->aux_usage = ISL_AUX_USAGE_CCS_D;
}
- } else if (intel_miptree_supports_hiz(brw, mt)) {
+ } else if (intel_tiling_supports_hiz(brw, mt) &&
+ intel_miptree_supports_hiz(brw, mt)) {
mt->aux_usage = ISL_AUX_USAGE_HIZ;
}
--
2.5.0.400.gff86faf
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