The HW can only write a 64b immediate into a 64b aligned address, so
add an assert.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 28c2f474c0..7af7d9b0a3 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -1014,6 +1014,7 @@ brw_store_data_imm64(struct brw_context *brw, struct
brw_bo *bo,
uint32_t offset, uint64_t imm)
{
assert(brw->gen >= 6);
+ assert((offset & 7) == 0);
BEGIN_BATCH(5);
OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
--
2.13.3
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