On 07/25/2017 05:19 AM, Christian König wrote:
Am 25.07.2017 um 08:27 schrieb Michel Dänzer:
On 25/07/17 02:54 AM, Leo Liu wrote:
To workaround an unknown bug.
Signed-off-by: Leo Liu <leo....@amd.com>
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index bd93b849db..a60b969a27 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1237,8 +1237,9 @@ struct pipe_video_codec
*radeon_create_decoder(struct pipe_context *context,
unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
if (have_it(dec))
msg_fb_it_size += IT_SCALING_TABLE_SIZE;
+ /* use vram to improve performance, workaround an unknown
bug */
if (!rvid_create_buffer(dec->screen,
&dec->msg_fb_it_buffers[i],
- msg_fb_it_size, PIPE_USAGE_STAGING)) {
+ msg_fb_it_size, PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't allocated message buffers.\n");
goto error;
}
Does PIPE_USAGE_STREAM help as well? That would be system memory but
with write-combined CPU access, whereas PIPE_USAGE_STAGING is cacheable.
No, unfortunately not. It's a hardware bug which is independent of the
caching mode.
Leo can you limit this workaround to APUs? Shouldn't matter for dGPUs.
This change is on vcn_dec, and that is for Raven only now.
Additional to that I would rather like to have that in the kernel, so
that we can easily remove it when the correct workaround from the
hardware guys for this issue lands.
Do you mean disabling Gart Cacheable completely in kernel, and using
VRAM globally instead? if that's the case, not sure if it would have
side effect on other part of the driver.
On the current issue, Msg buffer and Bitstream buffer are both in Gart,
but only Msg buffer affect the performance, since it interacts more
often with GPU.
Leo
Christian.
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