I commented on patch 42. Other than that, patches 40-73 are:
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Marek
On Wed, Jul 5, 2017 at 12:48 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haeh...@amd.com>
>
> Also, disable geometry and tessellation shaders. Mixing and matching NIR
> and TGSI shaders should work (and I've tested it for the VS/PS interface),
> but geometry and tessellation requires VS-as-ES/LS, which isn't implemented
> yet for NIR.
> ---
> src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
> src/gallium/drivers/radeon/r600_pipe_common.h | 2 +-
> src/gallium/drivers/radeonsi/si_pipe.c | 6 ++++++
> 3 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index fd67d9a..7a2a54b 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -723,20 +723,21 @@ void r600_common_context_cleanup(struct
> r600_common_context *rctx)
> rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
> }
>
> /*
> * pipe_screen
> */
>
> static const struct debug_named_value common_debug_options[] = {
> /* logging */
> { "tex", DBG_TEX, "Print texture info" },
> + { "nir", DBG_NIR, "Enable experimental NIR shaders" },
> { "compute", DBG_COMPUTE, "Print compute info" },
> { "vm", DBG_VM, "Print virtual addresses when creating resources" },
> { "info", DBG_INFO, "Print driver information" },
>
> /* shaders */
> { "fs", DBG_FS, "Print fetch shaders" },
> { "vs", DBG_VS, "Print vertex shaders" },
> { "gs", DBG_GS, "Print geometry shaders" },
> { "ps", DBG_PS, "Print pixel shaders" },
> { "cs", DBG_CS, "Print compute shaders" },
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index b22a3a7..64588eb 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -60,21 +60,21 @@
> #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
> #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
> #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
>
> /* special primitive types */
> #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
>
> /* Debug flags. */
> /* logging */
> #define DBG_TEX (1 << 0)
> -/* gap - reuse */
> +#define DBG_NIR (1 << 1)
> #define DBG_COMPUTE (1 << 2)
> #define DBG_VM (1 << 3)
> /* gap - reuse */
> /* shader logging */
> #define DBG_FS (1 << 5)
> #define DBG_VS (1 << 6)
> #define DBG_GS (1 << 7)
> #define DBG_PS (1 << 8)
> #define DBG_CS (1 << 9)
> #define DBG_TCS (1 << 10)
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index beadb88..2c2e66b 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -544,20 +544,22 @@ static int si_get_param(struct pipe_screen* pscreen,
> enum pipe_cap param)
>
> case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
> case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
> case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
> case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
> case PIPE_CAP_MAX_VERTEX_STREAMS:
> case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
> return 4;
>
> case PIPE_CAP_GLSL_FEATURE_LEVEL:
> + if (sscreen->b.debug_flags & DBG_NIR)
> + return 140; /* no geometry and tessellation shaders
> yet */
> if (si_have_tgsi_compute(sscreen))
> return 450;
> return 420;
>
> case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
> return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
>
> case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
> case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
> case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
> @@ -746,20 +748,24 @@ static int si_get_shader_param(struct pipe_screen*
> pscreen,
> case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
> case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
> return SI_NUM_SAMPLERS;
> case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
> return SI_NUM_SHADER_BUFFERS;
> case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
> return SI_NUM_IMAGES;
> case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
> return 32;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> + if (sscreen->b.debug_flags & DBG_NIR &&
> + (shader == PIPE_SHADER_VERTEX ||
> + shader == PIPE_SHADER_FRAGMENT))
> + return PIPE_SHADER_IR_NIR;
> return PIPE_SHADER_IR_TGSI;
> case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
> return 3;
>
> /* Supported boolean features. */
> case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
> case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
> case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
> case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
> --
> 2.9.3
>
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