From: Marek Olšák <[email protected]>
Gfx9 will use it too.
---
src/amd/common/ac_surface.c | 5 ++++-
src/amd/common/ac_surface.h | 16 +++++++++++++++-
src/amd/vulkan/radv_device.c | 6 +++---
src/amd/vulkan/radv_image.c | 6 +++---
4 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 26f3729..4647ce4 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -709,21 +709,24 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
AddrBaseSwizzleIn.surfIndex = config->info.surf_index;
AddrBaseSwizzleIn.tileIndex = AddrSurfInfoIn.tileIndex;
AddrBaseSwizzleIn.macroModeIndex =
AddrSurfInfoOut.macroModeIndex;
AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo;
AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode;
AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn,
&AddrBaseSwizzleOut);
- surf->u.legacy.tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
+
+ assert(AddrBaseSwizzleOut.tileSwizzle <=
+ u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
+ surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
}
return 0;
}
/* This is only called when expecting a tiled layout. */
static int
gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
bool is_fmask, AddrSwizzleMode *swizzle_mode)
{
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 3eaef63..ee96003 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -90,21 +90,20 @@ struct legacy_surf_layout {
unsigned macro_tile_index:4; /* max 15 */
/* Whether the depth miptree or stencil miptree as used by the DB are
* adjusted from their TC compatible form to ensure depth/stencil
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
unsigned depth_adjusted:1;
unsigned stencil_adjusted:1;
- uint8_t tile_swizzle;
struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS];
struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
};
/* Same as addrlib - AddrResourceType. */
enum gfx9_resource_type {
RADEON_RESOURCE_1D = 0,
RADEON_RESOURCE_2D,
@@ -161,20 +160,35 @@ struct radeon_surf {
unsigned num_dcc_levels:4;
unsigned is_linear:1;
/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
unsigned micro_tile_mode:3;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
* they will be treated as hints (e.g. bankw, bankh) and might be
* changed by the calculator.
*/
+
+ /* Tile swizzle can be OR'd with low bits of the BASE_256B address.
+ * The value is the same for all mipmap levels. Supported tile modes:
+ * - GFX6: Only macro tiling.
+ * - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail.
+ *
+ * Only these surfaces are allowed to set it:
+ * - color (if it doesn't have to be displayable)
+ * - DCC (same tile swizzle as color)
+ * - FMASK
+ * - CMASK if it's TC-compatible or if the gen is GFX9
+ * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
+ */
+ uint8_t tile_swizzle;
+
uint64_t surf_size;
uint64_t dcc_size;
uint64_t htile_size;
uint32_t htile_slice_size;
uint32_t surf_alignment;
uint32_t dcc_alignment;
uint32_t htile_alignment;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 19f1e10..57081e4 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2998,48 +2998,48 @@ radv_initialise_color_surface(struct radv_device
*device,
/* This must be set for fast clear to work without
FMASK. */
if (device->physical_device->rad_info.chip_class >= CIK)
cb->cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(pitch_tile_max);
cb->cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
cb->cb_color_fmask_slice =
S_028C88_TILE_MAX(slice_tile_max);
}
}
cb->cb_color_base = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
- cb->cb_color_base |=
iview->image->surface.u.legacy.tile_swizzle;
+ cb->cb_color_base |= iview->image->surface.tile_swizzle;
/* CMASK variables */
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->cmask.offset;
cb->cb_color_cmask = va >> 8;
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->dcc_offset;
cb->cb_dcc_base = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
- cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle;
+ cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
uint32_t max_slice = radv_surface_layer_count(iview);
cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
if (iview->image->info.samples > 1) {
unsigned log_samples =
util_logbase2(iview->image->info.samples);
cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_samples);
}
if (iview->image->fmask.size) {
va = device->ws->buffer_get_va(iview->bo) +
iview->image->offset + iview->image->fmask.offset;
cb->cb_color_fmask = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
- cb->cb_color_fmask |=
iview->image->surface.u.legacy.tile_swizzle;
+ cb->cb_color_fmask |=
iview->image->surface.tile_swizzle;
} else {
cb->cb_color_fmask = cb->cb_color_base;
}
ntype = radv_translate_color_numformat(iview->vk_format,
desc,
vk_format_get_first_non_void_channel(iview->vk_format));
format = radv_translate_colorformat(iview->vk_format);
if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
radv_finishme("Illegal color\n");
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ce1ee24..4b47e17 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -211,38 +211,38 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (chip_class >= GFX9) {
if (is_stencil)
va += image->surface.u.gfx9.stencil_offset;
else
va += image->surface.u.gfx9.surf_offset;
} else
va += base_level_info->offset;
state[0] = va >> 8;
if (chip_class < GFX9)
- state[0] |= image->surface.u.legacy.tile_swizzle;
+ state[0] |= image->surface.tile_swizzle;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
is_stencil));
state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
if (chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
if (image->surface.dcc_size && first_level <
image->surface.num_dcc_levels) {
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= VI)
meta_va += base_level_info->dcc_offset;
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
if (chip_class < GFX9)
- state[7] |=
image->surface.u.legacy.tile_swizzle;
+ state[7] |= image->surface.tile_swizzle;
}
}
if (chip_class >= GFX9) {
state[3] &= C_008F1C_SW_MODE;
state[4] &= C_008F20_PITCH_GFX9;
if (is_stencil) {
state[3] |=
S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
state[4] |=
S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
@@ -477,21 +477,21 @@ si_make_texture_descriptor(struct radv_device *device,
break;
default:
assert(0);
fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
}
num_format = V_008F14_IMG_NUM_FORMAT_UINT;
}
fmask_state[0] = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
- fmask_state[0] |= image->surface.u.legacy.tile_swizzle;
+ fmask_state[0] |= image->surface.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(fmask_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);
fmask_state[2] = S_008F18_WIDTH(width - 1) |
S_008F18_HEIGHT(height - 1);
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1,
0, false));
--
2.7.4
_______________________________________________
mesa-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
