From: Marek Olšák <[email protected]>
Mipmapping with tile swizzle doesn't work.
---
src/amd/common/ac_surface.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 87a8993..3716d3d 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -428,21 +428,23 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib,
surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
surf->u.legacy.num_banks = csio->pTileInfo->banks;
surf->u.legacy.macro_tile_index = csio->macroModeIndex;
} else {
surf->u.legacy.macro_tile_index = 0;
}
/* Compute tile swizzle. */
- if (config->info.surf_index &&
+ /* TODO: fix tile swizzle with mipmapping for SI */
+ if ((info->chip_class >= CIK || config->info.levels == 1) &&
+ config->info.surf_index &&
surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
!(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE))
&&
(config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT)))
{
ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
AddrBaseSwizzleIn.size =
sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
AddrBaseSwizzleOut.size =
sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
AddrBaseSwizzleIn.surfIndex =
p_atomic_inc_return(config->info.surf_index) - 1;
--
2.7.4
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