From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 1 -
src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c | 1 -
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 43 ---------------------
src/gallium/auxiliary/nir/tgsi_to_nir.c | 3 --
src/gallium/auxiliary/tgsi/tgsi_exec.c | 19 ---------
src/gallium/auxiliary/tgsi/tgsi_info.c | 5 +--
src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h | 1 -
src/gallium/docs/source/tgsi.rst | 16 +-------
src/gallium/drivers/r300/r300_tgsi_to_rc.c | 1 -
src/gallium/drivers/r600/r600_shader.c | 45 ++--------------------
src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 2 -
src/gallium/include/pipe/p_shader_tokens.h | 1 -
src/gallium/state_trackers/nine/nine_shader.c | 2 +-
13 files changed, 7 insertions(+), 133 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index 4b8b7c8..ce2b927 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -1165,21 +1165,20 @@ lp_set_default_actions(struct lp_build_tgsi_context *
bld_base)
bld_base->op_actions[TGSI_OPCODE_DST] = dst_action;
bld_base->op_actions[TGSI_OPCODE_EXP] = exp_action;
bld_base->op_actions[TGSI_OPCODE_LIT] = lit_action;
bld_base->op_actions[TGSI_OPCODE_LOG] = log_action;
bld_base->op_actions[TGSI_OPCODE_PK2H] = pk2h_action;
bld_base->op_actions[TGSI_OPCODE_RSQ] = rsq_action;
bld_base->op_actions[TGSI_OPCODE_SQRT] = sqrt_action;
bld_base->op_actions[TGSI_OPCODE_POW] = pow_action;
bld_base->op_actions[TGSI_OPCODE_UP2H] = up2h_action;
- bld_base->op_actions[TGSI_OPCODE_BREAKC].fetch_args =
scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_SWITCH].fetch_args =
scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_CASE].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_COS].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_EX2].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_IF].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_UIF].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kil_fetch_args;
bld_base->op_actions[TGSI_OPCODE_KILL].fetch_args = kilp_fetch_args;
bld_base->op_actions[TGSI_OPCODE_RCP].fetch_args = scalar_unary_fetch_args;
bld_base->op_actions[TGSI_OPCODE_SIN].fetch_args = scalar_unary_fetch_args;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
index c3ed1ee..b4e3c2f 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_info.c
@@ -431,21 +431,20 @@ analyse_instruction(struct analysis_context *ctx,
* Clear all temporaries information in presence of a control flow opcode.
*/
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_IF:
case TGSI_OPCODE_UIF:
case TGSI_OPCODE_ELSE:
case TGSI_OPCODE_ENDIF:
case TGSI_OPCODE_BGNLOOP:
case TGSI_OPCODE_BRK:
- case TGSI_OPCODE_BREAKC:
case TGSI_OPCODE_CONT:
case TGSI_OPCODE_ENDLOOP:
case TGSI_OPCODE_CAL:
case TGSI_OPCODE_BGNSUB:
case TGSI_OPCODE_ENDSUB:
case TGSI_OPCODE_SWITCH:
case TGSI_OPCODE_CASE:
case TGSI_OPCODE_DEFAULT:
case TGSI_OPCODE_ENDSWITCH:
case TGSI_OPCODE_RET:
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index d838e28..b7f1140 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -395,44 +395,20 @@ static void lp_exec_break(struct lp_exec_mask *mask,
"break");
mask->switch_mask = LLVMBuildAnd(builder,
mask->switch_mask,
exec_mask, "break_switch");
}
}
lp_exec_mask_update(mask);
}
-static void lp_exec_break_condition(struct lp_exec_mask *mask,
- LLVMValueRef cond)
-{
- LLVMBuilderRef builder = mask->bld->gallivm->builder;
- struct function_ctx *ctx = func_ctx(mask);
- LLVMValueRef cond_mask = LLVMBuildAnd(builder,
- mask->exec_mask,
- cond, "cond_mask");
- cond_mask = LLVMBuildNot(builder, cond_mask, "break_cond");
-
- if (ctx->break_type == LP_EXEC_MASK_BREAK_TYPE_LOOP) {
- mask->break_mask = LLVMBuildAnd(builder,
- mask->break_mask,
- cond_mask, "breakc_full");
- }
- else {
- mask->switch_mask = LLVMBuildAnd(builder,
- mask->switch_mask,
- cond_mask, "breakc_switch");
- }
-
- lp_exec_mask_update(mask);
-}
-
static void lp_exec_continue(struct lp_exec_mask *mask)
{
LLVMBuilderRef builder = mask->bld->gallivm->builder;
LLVMValueRef exec_mask = LLVMBuildNot(builder,
mask->exec_mask,
"");
mask->cont_mask = LLVMBuildAnd(builder,
mask->cont_mask,
exec_mask, "");
@@ -3471,38 +3447,20 @@ brk_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
lp_exec_break(&bld->exec_mask, bld_base);
}
static void
-breakc_emit(
- const struct lp_build_tgsi_action * action,
- struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
-{
- struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
- LLVMBuilderRef builder = bld_base->base.gallivm->builder;
- struct lp_build_context *uint_bld = &bld_base->uint_bld;
- LLVMValueRef unsigned_cond =
- LLVMBuildBitCast(builder, emit_data->args[0], uint_bld->vec_type, "");
- LLVMValueRef cond = lp_build_cmp(uint_bld, PIPE_FUNC_NOTEQUAL,
- unsigned_cond,
- uint_bld->zero);
-
- lp_exec_break_condition(&bld->exec_mask, cond);
-}
-
-static void
if_emit(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMValueRef tmp;
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
tmp = lp_build_cmp(&bld_base->base, PIPE_FUNC_NOTEQUAL,
emit_data->args[0], bld->bld_base.base.zero);
@@ -3869,21 +3827,20 @@ lp_build_tgsi_soa(struct gallivm_state *gallivm,
bld.bld_base.emit_prologue = emit_prologue;
bld.bld_base.emit_epilogue = emit_epilogue;
/* Set opcode actions */
lp_set_default_actions_cpu(&bld.bld_base);
bld.bld_base.op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
bld.bld_base.op_actions[TGSI_OPCODE_BGNSUB].emit = bgnsub_emit;
bld.bld_base.op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
- bld.bld_base.op_actions[TGSI_OPCODE_BREAKC].emit = breakc_emit;
bld.bld_base.op_actions[TGSI_OPCODE_CAL].emit = cal_emit;
bld.bld_base.op_actions[TGSI_OPCODE_CASE].emit = case_emit;
bld.bld_base.op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
bld.bld_base.op_actions[TGSI_OPCODE_DDX].emit = ddx_emit;
bld.bld_base.op_actions[TGSI_OPCODE_DDY].emit = ddy_emit;
bld.bld_base.op_actions[TGSI_OPCODE_DEFAULT].emit = default_emit;
bld.bld_base.op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
bld.bld_base.op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
bld.bld_base.op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
bld.bld_base.op_actions[TGSI_OPCODE_ENDSUB].emit = endsub_emit;
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 62f8feb..733eca0 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1557,23 +1557,20 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
[TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
[TGSI_OPCODE_ENDLOOP] = 0,
[TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
[TGSI_OPCODE_NOP] = 0,
[TGSI_OPCODE_FSEQ] = nir_op_feq,
[TGSI_OPCODE_FSGE] = nir_op_fge,
[TGSI_OPCODE_FSLT] = nir_op_flt,
[TGSI_OPCODE_FSNE] = nir_op_fne,
- /* No control flow yet */
- [TGSI_OPCODE_BREAKC] = 0, /* not emitted by glsl_to_tgsi.cpp */
-
[TGSI_OPCODE_KILL_IF] = 0,
[TGSI_OPCODE_END] = 0,
[TGSI_OPCODE_F2I] = nir_op_f2i32,
[TGSI_OPCODE_IDIV] = nir_op_idiv,
[TGSI_OPCODE_IMAX] = nir_op_imax,
[TGSI_OPCODE_IMIN] = nir_op_imin,
[TGSI_OPCODE_INEG] = nir_op_ineg,
[TGSI_OPCODE_ISGE] = nir_op_ige,
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index b7ec309..c58ea6a 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -5519,39 +5519,20 @@ exec_instruction(
mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
*pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
UPDATE_EXEC_MASK(mach);
break;
case TGSI_OPCODE_NOP:
break;
- case TGSI_OPCODE_BREAKC:
- IFETCH(&r[0], 0, TGSI_CHAN_X);
- /* update CondMask */
- if (r[0].u[0] && (mach->ExecMask & 0x1)) {
- mach->LoopMask &= ~0x1;
- }
- if (r[0].u[1] && (mach->ExecMask & 0x2)) {
- mach->LoopMask &= ~0x2;
- }
- if (r[0].u[2] && (mach->ExecMask & 0x4)) {
- mach->LoopMask &= ~0x4;
- }
- if (r[0].u[3] && (mach->ExecMask & 0x8)) {
- mach->LoopMask &= ~0x8;
- }
- /* Todo: if mach->LoopMask == 0, jump to end of loop */
- UPDATE_EXEC_MASK(mach);
- break;
-
case TGSI_OPCODE_F2I:
exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT,
TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_FSEQ:
exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT,
TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_FSGE:
exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT,
TGSI_EXEC_DATA_FLOAT);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 6d36e40..0a82dbb 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -144,22 +144,22 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 1, 1, 0, 0, 0, 0, OTHR, "TXQS", TGSI_OPCODE_TXQS },
{ 1, 1, 0, 0, 0, 0, 0, OTHR, "RESQ", TGSI_OPCODE_RESQ },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "READ_FIRST", TGSI_OPCODE_READ_FIRST },
{ 0, 0, 0, 0, 0, 0, 0, NONE, "NOP", TGSI_OPCODE_NOP },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "FSEQ", TGSI_OPCODE_FSEQ },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "FSGE", TGSI_OPCODE_FSGE },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "FSLT", TGSI_OPCODE_FSLT },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "FSNE", TGSI_OPCODE_FSNE },
{ 0, 1, 0, 0, 0, 0, 0, OTHR, "MEMBAR", TGSI_OPCODE_MEMBAR },
{ 0, 1, 0, 0, 0, 0, 0, NONE, "", 113 }, /* removed */
- { 0, 1, 0, 0, 0, 0, 0, NONE, "", 114 }, /* removed */
- { 0, 1, 0, 0, 0, 0, 0, NONE, "BREAKC", TGSI_OPCODE_BREAKC },
+ { 0, 1, 0, 0, 0, 0, 0, NONE, "", 114 }, /* removed */
+ { 0, 1, 0, 0, 0, 0, 0, NONE, "", 115 }, /* removed */
{ 0, 1, 0, 0, 0, 0, 0, NONE, "KILL_IF", TGSI_OPCODE_KILL_IF },
{ 0, 0, 0, 0, 0, 0, 0, NONE, "END", TGSI_OPCODE_END },
{ 1, 3, 0, 0, 0, 0, 0, COMP, "DFMA", TGSI_OPCODE_DFMA },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2I", TGSI_OPCODE_F2I },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "IDIV", TGSI_OPCODE_IDIV },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "IMAX", TGSI_OPCODE_IMAX },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "IMIN", TGSI_OPCODE_IMIN },
{ 1, 1, 0, 0, 0, 0, 0, COMP, "INEG", TGSI_OPCODE_INEG },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "ISGE", TGSI_OPCODE_ISGE },
{ 1, 2, 0, 0, 0, 0, 0, COMP, "ISHR", TGSI_OPCODE_ISHR },
@@ -470,21 +470,20 @@ tgsi_opcode_infer_type( uint opcode )
/*
* infer the source type of a TGSI opcode.
*/
enum tgsi_opcode_type
tgsi_opcode_infer_src_type( uint opcode )
{
switch (opcode) {
case TGSI_OPCODE_UIF:
case TGSI_OPCODE_TXF:
case TGSI_OPCODE_TXF_LZ:
- case TGSI_OPCODE_BREAKC:
case TGSI_OPCODE_U2F:
case TGSI_OPCODE_U2D:
case TGSI_OPCODE_UADD:
case TGSI_OPCODE_SWITCH:
case TGSI_OPCODE_CASE:
case TGSI_OPCODE_SAMPLE_I:
case TGSI_OPCODE_SAMPLE_I_MS:
case TGSI_OPCODE_UMUL_HI:
case TGSI_OPCODE_UP2H:
case TGSI_OPCODE_U2I64:
diff --git a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
index 895e0b0..9a13fa6 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h
@@ -111,21 +111,20 @@ OP12(XOR)
OP12_TEX(TXF)
OP12_TEX(TXQ)
OP00(CONT)
OP01(EMIT)
OP01(ENDPRIM)
OP00_LBL(BGNLOOP)
OP00(BGNSUB)
OP00_LBL(ENDLOOP)
OP00(ENDSUB)
OP00(NOP)
-OP01(BREAKC)
OP01(KILL_IF)
OP00(END)
OP11(F2I)
OP12(FSEQ)
OP12(FSGE)
OP12(FSLT)
OP12(FSNE)
OP12(IDIV)
OP12(IMAX)
OP12(IMIN)
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 8441316..b148c3c 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1576,21 +1576,21 @@ in any other type of shader.
Complete the current primitive in the specified vertex stream (consisting of
the emitted vertices), and start a new one.
GLSL ISA
^^^^^^^^^^
These opcodes are part of :term:`GLSL`'s opcode set. Support for these
opcodes is determined by a special capability bit, ``GLSL``.
-Some require glsl version 1.30 (UIF/BREAKC/SWITCH/CASE/DEFAULT/ENDSWITCH).
+Some require glsl version 1.30 (UIF/SWITCH/CASE/DEFAULT/ENDSWITCH).
.. opcode:: CAL - Subroutine Call
push(pc)
pc = target
.. opcode:: RET - Subroutine Call Return
pc = pop()
@@ -1632,34 +1632,20 @@ Some require glsl version 1.30
(UIF/BREAKC/SWITCH/CASE/DEFAULT/ENDSWITCH).
Do nothing.
.. opcode:: BRK - Break
Unconditionally moves the point of execution to the instruction after the
next endloop or endswitch. The instruction must appear within a loop/endloop
or switch/endswitch.
-.. opcode:: BREAKC - Break Conditional
-
- Conditionally moves the point of execution to the instruction after the
- next endloop or endswitch. The instruction must appear within a loop/endloop
- or switch/endswitch.
- Condition evaluates to true if src0.x != 0 where src0.x is interpreted
- as an integer register.
-
-.. note::
-
- Considered for removal as it's quite inconsistent wrt other opcodes
- (could emulate with UIF/BRK/ENDIF).
-
-
.. opcode:: IF - Float If
Start an IF ... ELSE .. ENDIF block. Condition evaluates to true if
src0.x != 0.0
where src0.x is interpreted as a floating point register.
.. opcode:: UIF - Bitwise If
diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
index a21a714..3030698 100644
--- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
+++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
@@ -107,21 +107,20 @@ static unsigned translate_opcode(unsigned opcode)
/* case TGSI_OPCODE_TXF: return RC_OPCODE_TXF; */
/* case TGSI_OPCODE_TXQ: return RC_OPCODE_TXQ; */
case TGSI_OPCODE_CONT: return RC_OPCODE_CONT;
/* case TGSI_OPCODE_EMIT: return RC_OPCODE_EMIT; */
/* case TGSI_OPCODE_ENDPRIM: return RC_OPCODE_ENDPRIM; */
/* case TGSI_OPCODE_BGNLOOP2: return RC_OPCODE_BGNLOOP2; */
/* case TGSI_OPCODE_BGNSUB: return RC_OPCODE_BGNSUB; */
/* case TGSI_OPCODE_ENDLOOP2: return RC_OPCODE_ENDLOOP2; */
/* case TGSI_OPCODE_ENDSUB: return RC_OPCODE_ENDSUB; */
case TGSI_OPCODE_NOP: return RC_OPCODE_NOP;
- /* case TGSI_OPCODE_BREAKC: return RC_OPCODE_BREAKC; */
case TGSI_OPCODE_KILL_IF: return RC_OPCODE_KIL;
}
fprintf(stderr, "r300: Unknown TGSI/RC opcode: %s\n",
tgsi_get_opcode_name(opcode));
return RC_OPCODE_ILLEGAL_OPCODE;
}
static unsigned translate_saturate(unsigned saturate)
{
return saturate ? RC_SATURATE_ZERO_ONE : RC_SATURATE_NONE;
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 45d256c..c9c922f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -8605,59 +8605,20 @@ static int tgsi_endloop(struct r600_shader_ctx *ctx)
for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr =
ctx->bc->cf_last->id;
}
/* XXX add LOOPRET support */
fc_poplevel(ctx);
callstack_pop(ctx, FC_LOOP);
return 0;
}
-static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
-{
- int r;
- unsigned int fscp;
-
- for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
- {
- if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
- break;
- }
- if (fscp == 0) {
- R600_ERR("BREAKC not inside loop/endloop pair\n");
- return -EINVAL;
- }
-
- if (ctx->bc->chip_class == EVERGREEN &&
- ctx->bc->family != CHIP_CYPRESS &&
- ctx->bc->family != CHIP_JUNIPER) {
- /* HW bug: ALU_BREAK does not save the active mask correctly */
- r = tgsi_uif(ctx);
- if (r)
- return r;
-
- r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
- if (r)
- return r;
- fc_set_mid(ctx, fscp - 1);
-
- return tgsi_endif(ctx);
- } else {
- r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT,
CF_OP_ALU_BREAK);
- if (r)
- return r;
- fc_set_mid(ctx, fscp - 1);
- }
-
- return 0;
-}
-
static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
{
unsigned int fscp;
for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
{
if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
break;
}
@@ -8976,21 +8937,21 @@ static const struct r600_shader_tgsi_instruction
r600_shader_tgsi_instruction[]
[TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
[106] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
[TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
[TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
[TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
[113] = { ALU_OP0_NOP, tgsi_unsupported},
[114] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
+ [115] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional
kill */
[TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
[TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
[TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
[TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
[TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
[TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
[TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
[TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
@@ -9174,21 +9135,21 @@ static const struct r600_shader_tgsi_instruction
eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
[106] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
[TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
[TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
[TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
[113] = { ALU_OP0_NOP, tgsi_unsupported},
[114] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
+ [115] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional
kill */
[TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
/* Refer below for TGSI_OPCODE_DFMA */
[TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
[TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
[TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
[TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
[TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
[TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
[TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
@@ -9397,21 +9358,21 @@ static const struct r600_shader_tgsi_instruction
cm_shader_tgsi_instruction[] =
[TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
[106] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
[TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
[TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
[TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
[TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
[113] = { ALU_OP0_NOP, tgsi_unsupported},
[114] = { ALU_OP0_NOP, tgsi_unsupported},
- [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
+ [115] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional
kill */
[TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
/* Refer below for TGSI_OPCODE_DFMA */
[TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
[TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
[TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
[TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
[TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
[TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
[TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index ac312b1..a864616 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -571,22 +571,20 @@ translate_opcode(unsigned opcode)
case TGSI_OPCODE_ENDPRIM:
return VGPU10_OPCODE_CUT;
case TGSI_OPCODE_BGNLOOP:
return VGPU10_OPCODE_LOOP;
case TGSI_OPCODE_ENDLOOP:
return VGPU10_OPCODE_ENDLOOP;
case TGSI_OPCODE_ENDSUB:
return VGPU10_OPCODE_RET;
case TGSI_OPCODE_NOP:
return VGPU10_OPCODE_NOP;
- case TGSI_OPCODE_BREAKC:
- return VGPU10_OPCODE_BREAKC;
case TGSI_OPCODE_END:
return VGPU10_OPCODE_RET;
case TGSI_OPCODE_F2I:
return VGPU10_OPCODE_FTOI;
case TGSI_OPCODE_IMAX:
return VGPU10_OPCODE_IMAX;
case TGSI_OPCODE_IMIN:
return VGPU10_OPCODE_IMIN;
case TGSI_OPCODE_UDIV:
case TGSI_OPCODE_UMOD:
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index ae36a1e..9648f5a 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -446,21 +446,20 @@ struct tgsi_property_data {
#define TGSI_OPCODE_READ_FIRST 106
#define TGSI_OPCODE_NOP 107
#define TGSI_OPCODE_FSEQ 108
#define TGSI_OPCODE_FSGE 109
#define TGSI_OPCODE_FSLT 110
#define TGSI_OPCODE_FSNE 111
#define TGSI_OPCODE_MEMBAR 112
/* gap */
-#define TGSI_OPCODE_BREAKC 115
#define TGSI_OPCODE_KILL_IF 116 /* conditional kill */
#define TGSI_OPCODE_END 117 /* aka HALT */
#define TGSI_OPCODE_DFMA 118
#define TGSI_OPCODE_F2I 119
#define TGSI_OPCODE_IDIV 120
#define TGSI_OPCODE_IMAX 121
#define TGSI_OPCODE_IMIN 122
#define TGSI_OPCODE_INEG 123
#define TGSI_OPCODE_ISGE 124
#define TGSI_OPCODE_ISHR 125
diff --git a/src/gallium/state_trackers/nine/nine_shader.c
b/src/gallium/state_trackers/nine/nine_shader.c
index fae06aa..5b60dcb 100644
--- a/src/gallium/state_trackers/nine/nine_shader.c
+++ b/src/gallium/state_trackers/nine/nine_shader.c
@@ -2951,21 +2951,21 @@ struct sm1_op_info inst_table[] =
_OPI(SINCOS, NOP, V(3,0), V(3,0), V(3,0), V(3,0), 1, 1, SPECIAL(SINCOS)),
/* More flow control */
_OPI(REP, NOP, V(2,0), V(3,0), V(2,1), V(3,0), 0, 1, SPECIAL(REP)),
_OPI(ENDREP, NOP, V(2,0), V(3,0), V(2,1), V(3,0), 0, 0,
SPECIAL(ENDREP)),
_OPI(IF, IF, V(2,0), V(3,0), V(2,1), V(3,0), 0, 1, SPECIAL(IF)),
_OPI(IFC, IF, V(2,1), V(3,0), V(2,1), V(3,0), 0, 2, SPECIAL(IFC)),
_OPI(ELSE, ELSE, V(2,0), V(3,0), V(2,1), V(3,0), 0, 0, SPECIAL(ELSE)),
_OPI(ENDIF, ENDIF, V(2,0), V(3,0), V(2,1), V(3,0), 0, 0, SPECIAL(ENDIF)),
_OPI(BREAK, BRK, V(2,1), V(3,0), V(2,1), V(3,0), 0, 0, NULL),
- _OPI(BREAKC, BREAKC, V(2,1), V(3,0), V(2,1), V(3,0), 0, 2,
SPECIAL(BREAKC)),
+ _OPI(BREAKC, NOP, V(2,1), V(3,0), V(2,1), V(3,0), 0, 2,
SPECIAL(BREAKC)),
/* we don't write to the address register, but a normal register (copied
* when needed to the address register), thus we don't use ARR */
_OPI(MOVA, MOV, V(2,0), V(3,0), V(0,0), V(0,0), 1, 1, NULL),
_OPI(DEFB, NOP, V(0,0), V(3,0) , V(0,0), V(3,0) , 1, 0, SPECIAL(DEFB)),
_OPI(DEFI, NOP, V(0,0), V(3,0) , V(0,0), V(3,0) , 1, 0, SPECIAL(DEFI)),
_OPI(TEXCOORD, NOP, V(0,0), V(0,0), V(0,0), V(1,3), 1, 0,
SPECIAL(TEXCOORD)),
_OPI(TEXCOORD, MOV, V(0,0), V(0,0), V(1,4), V(1,4), 1, 1,
SPECIAL(TEXCOORD_ps14)),
_OPI(TEXKILL, KILL_IF, V(0,0), V(0,0), V(0,0), V(3,0), 1, 0,
SPECIAL(TEXKILL)),
--
2.7.4
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
