This little series contains some fixes I found when working on SPIR-V subgroup operations. From my reading of GL_ARB_shader_ballot, the readInvocationARB and readFirstInvocationARB intrinsics only support 32-bit values. This seems weird to me, but whatever. The SPIR-V subgroup extensions, on the other hand, have no such restriction. This little series fixes the back-end implementation to work for 64-bit types. It's also generally a clean-up so I think it's ok to land now.
Alejandro Piñeiro (1): i965/fs: Add brw_reg_type_from_bit_size utility method Jason Ekstrand (6): i965/fs/nir: Use the nir_src_bit_size helper i965/fs/nir: Simplify 64-bit store_output i965/fs: Return a fs_reg from shuffle_64bit_data_for_32bit_write i965/fs/nir: Minor refactor of store_output i965/fs/nir: Don't stomp 64-bit values to D in get_nir_src i965/fs: Fix readInvocationARB and readFirstInvocationARB src/intel/compiler/brw_fs.h | 7 +- src/intel/compiler/brw_fs_nir.cpp | 202 +++++++++++++++++++++++--------------- 2 files changed, 127 insertions(+), 82 deletions(-) -- 2.5.0.400.gff86faf _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
