From: Nicolai Hähnle <[email protected]>
They are just copies of the rasterizer state.
---
src/gallium/drivers/radeonsi/si_pipe.h | 4 ----
src/gallium/drivers/radeonsi/si_state.c | 14 +++++++++++--
src/gallium/drivers/radeonsi/si_viewport.c | 32 +++++++++++-------------------
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 4fe158fb9af..ed88aa0521b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -455,22 +455,20 @@ struct si_context {
/* Debug state. */
bool is_debug;
struct si_saved_cs *current_saved_cs;
uint64_t dmesg_timestamp;
unsigned apitrace_call_number;
/* Other state */
bool need_check_render_feedback;
bool decompression_enabled;
- bool scissor_enabled;
- bool clip_halfz;
bool vs_writes_viewport_index;
bool vs_disables_clipping_viewport;
/* Precomputed IA_MULTI_VGT_PARAM */
union si_vgt_param_key ia_multi_vgt_param_key;
unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
/* Bindless descriptors. */
struct si_descriptors bindless_descriptors;
struct util_idalloc bindless_used_slots;
@@ -560,22 +558,20 @@ void si_init_compute_functions(struct si_context *sctx);
void si_init_perfcounters(struct si_screen *screen);
/* si_uvd.c */
struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
const struct pipe_video_codec
*templ);
struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
const struct pipe_video_buffer
*tmpl);
/* si_viewport.c */
-void si_viewport_set_rast_deps(struct si_context *rctx,
- bool scissor_enable, bool clip_halfz);
void si_update_vs_writes_viewport_index(struct si_context *ctx);
void si_init_viewport_functions(struct si_context *ctx);
/*
* common helpers
*/
static inline void
si_invalidate_draw_sh_constants(struct si_context *sctx)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 2dbe7c6e274..78a3fbd086e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -996,26 +996,36 @@ static void si_bind_rs_state(struct pipe_context *ctx,
void *state)
/* Update the small primitive filter workaround if necessary. */
if (sctx->screen->has_msaa_sample_loc_bug &&
sctx->framebuffer.nr_samples > 1)
si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
}
sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
sctx->current_vs_state |=
S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
- si_viewport_set_rast_deps(sctx, rs->scissor_enable, rs->clip_halfz);
-
si_pm4_bind_state(sctx, rasterizer, rs);
si_update_poly_offset_state(sctx);
if (!old_rs ||
+ old_rs->scissor_enable != rs->scissor_enable) {
+ sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(sctx, &sctx->scissors.atom);
+ }
+
+ if (!old_rs ||
+ old_rs->clip_halfz != rs->clip_halfz) {
+ sctx->viewports.depth_range_dirty_mask = (1 <<
SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(sctx, &sctx->viewports.atom);
+ }
+
+ if (!old_rs ||
old_rs->clip_plane_enable != rs->clip_plane_enable ||
old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
si_mark_atom_dirty(sctx, &sctx->clip_regs);
sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
rs->line_stipple_enable;
if (!old_rs ||
old_rs->clip_plane_enable != rs->clip_plane_enable ||
old_rs->rasterizer_discard != rs->rasterizer_discard ||
diff --git a/src/gallium/drivers/radeonsi/si_viewport.c
b/src/gallium/drivers/radeonsi/si_viewport.c
index c4ffe385765..6a6b0823e13 100644
--- a/src/gallium/drivers/radeonsi/si_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_viewport.c
@@ -33,21 +33,22 @@ static void si_set_scissor_states(struct pipe_context *pctx,
unsigned start_slot,
unsigned num_scissors,
const struct pipe_scissor_state *state)
{
struct si_context *ctx = (struct si_context *)pctx;
int i;
for (i = 0; i < num_scissors; i++)
ctx->scissors.states[start_slot + i] = state[i];
- if (!ctx->scissor_enabled)
+ if (!ctx->queued.named.rasterizer ||
+ !ctx->queued.named.rasterizer->scissor_enable)
return;
ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
si_mark_atom_dirty(ctx, &ctx->scissors.atom);
}
/* Since the guard band disables clipping, we have to clip per-pixel
* using a scissor.
*/
static void si_get_scissor_from_viewport(struct si_context *ctx,
@@ -208,24 +209,27 @@ static void si_emit_guardband(struct si_context *ctx,
radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
}
static void si_emit_scissors(struct r600_common_context *rctx, struct
r600_atom *atom)
{
struct si_context *ctx = (struct si_context *)rctx;
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
struct pipe_scissor_state *states = ctx->scissors.states;
unsigned mask = ctx->scissors.dirty_mask;
- bool scissor_enabled = ctx->scissor_enabled;
+ bool scissor_enabled = false;
struct si_signed_scissor max_vp_scissor;
int i;
+ if (ctx->queued.named.rasterizer)
+ scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
+
/* The simple case: Only 1 viewport is active. */
if (!ctx->vs_writes_viewport_index) {
struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
if (!(mask & 1))
return;
radeon_set_context_reg_seq(cs,
R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] :
NULL);
si_emit_guardband(ctx, vp);
@@ -321,76 +325,64 @@ static void si_emit_viewports(struct si_context *ctx)
si_emit_one_viewport(ctx, &states[i]);
}
ctx->viewports.dirty_mask = 0;
}
static void si_emit_depth_ranges(struct si_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
struct pipe_viewport_state *states = ctx->viewports.states;
unsigned mask = ctx->viewports.depth_range_dirty_mask;
+ bool clip_halfz = false;
float zmin, zmax;
+ if (ctx->queued.named.rasterizer)
+ clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
+
/* The simple case: Only 1 viewport is active. */
if (!ctx->vs_writes_viewport_index) {
if (!(mask & 1))
return;
- util_viewport_zmin_zmax(&states[0], ctx->clip_halfz, &zmin,
&zmax);
+ util_viewport_zmin_zmax(&states[0], clip_halfz, &zmin, &zmax);
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
radeon_emit(cs, fui(zmin));
radeon_emit(cs, fui(zmax));
ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
return;
}
while (mask) {
int start, count, i;
u_bit_scan_consecutive_range(&mask, &start, &count);
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
start * 4 * 2, count * 2);
for (i = start; i < start+count; i++) {
- util_viewport_zmin_zmax(&states[i], ctx->clip_halfz,
&zmin, &zmax);
+ util_viewport_zmin_zmax(&states[i], clip_halfz, &zmin,
&zmax);
radeon_emit(cs, fui(zmin));
radeon_emit(cs, fui(zmax));
}
}
ctx->viewports.depth_range_dirty_mask = 0;
}
static void si_emit_viewport_states(struct r600_common_context *rctx,
struct r600_atom *atom)
{
struct si_context *ctx = (struct si_context *)rctx;
si_emit_viewports(ctx);
si_emit_depth_ranges(ctx);
}
-/* Set viewport dependencies on pipe_rasterizer_state. */
-void si_viewport_set_rast_deps(struct si_context *ctx,
- bool scissor_enable, bool clip_halfz)
-{
- if (ctx->scissor_enabled != scissor_enable) {
- ctx->scissor_enabled = scissor_enable;
- ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
- si_mark_atom_dirty(ctx, &ctx->scissors.atom);
- }
- if (ctx->clip_halfz != clip_halfz) {
- ctx->clip_halfz = clip_halfz;
- ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS)
- 1;
- si_mark_atom_dirty(ctx, &ctx->viewports.atom);
- }
-}
-
/**
* Normally, we only emit 1 viewport and 1 scissor if no shader is using
* the VIEWPORT_INDEX output, and emitting the other viewports and scissors
* is delayed. When a shader with VIEWPORT_INDEX appears, this should be
* called to emit the rest.
*/
void si_update_vs_writes_viewport_index(struct si_context *ctx)
{
struct tgsi_shader_info *info = si_get_vs_info(ctx);
bool vs_window_space;
--
2.11.0
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