On Thu, Sep 28, 2017 at 8:08 PM, Dave Airlie <[email protected]> wrote: > From: Dave Airlie <[email protected]> > > These don't seem to change at runtime, and the initialisers > are constant data. This could be improved by not selecting > the apu/non-apu path on each pcie read/write access. > > Signed-off-by: Dave Airlie <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 8 ++++---- > drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 2 +- > drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 8 ++++---- > drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 2 +- > drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- > 5 files changed, 12 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c > b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c > index 045988b..7723d7b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c > @@ -216,7 +216,10 @@ void nbio_v6_1_get_clockgating_state(struct > amdgpu_device *adev, u32 *flags) > } > > struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg; > -struct nbio_pcie_index_data nbio_v6_1_pcie_index_data; > +const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = { > + .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX), > + .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA), > +}; > > int nbio_v6_1_init(struct amdgpu_device *adev) > { > @@ -235,9 +238,6 @@ int nbio_v6_1_init(struct amdgpu_device *adev) > nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = > BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK; > nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = > BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK; > > - nbio_v6_1_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, > mmPCIE_INDEX); > - nbio_v6_1_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, > mmPCIE_DATA); > - > return 0; > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h > b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h > index 686e4b4..c5ca1e4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h > @@ -27,7 +27,7 @@ > #include "soc15_common.h" > > extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg; > -extern struct nbio_pcie_index_data nbio_v6_1_pcie_index_data; > +extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data; > int nbio_v6_1_init(struct amdgpu_device *adev); > u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, > uint32_t idx); > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c > b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c > index 11b70d6..b932b78 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c > @@ -186,7 +186,10 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev) > } > > struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg; > -struct nbio_pcie_index_data nbio_v7_0_pcie_index_data; > +const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data = { > + .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), > + .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2) > +}; > > int nbio_v7_0_init(struct amdgpu_device *adev) > { > @@ -205,8 +208,5 @@ int nbio_v7_0_init(struct amdgpu_device *adev) > nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = > GPU_HDP_FLUSH_DONE__SDMA0_MASK; > nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = > GPU_HDP_FLUSH_DONE__SDMA1_MASK; > > - nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, > mmPCIE_INDEX2); > - nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, > mmPCIE_DATA2); > - > return 0; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h > b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h > index 054ff49..21bad00 100644 > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h > @@ -27,7 +27,7 @@ > #include "soc15_common.h" > > extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg; > -extern struct nbio_pcie_index_data nbio_v7_0_pcie_index_data; > +extern const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data; > int nbio_v7_0_init(struct amdgpu_device *adev); > u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev, > uint32_t idx); > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c > b/drivers/gpu/drm/amd/amdgpu/soc15.c > index c2611ec..28294f5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c > @@ -101,7 +101,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, > u32 reg) > { > unsigned long flags, address, data; > u32 r; > - struct nbio_pcie_index_data *nbio_pcie_id; > + const struct nbio_pcie_index_data *nbio_pcie_id; > > if (adev->flags & AMD_IS_APU) > nbio_pcie_id = &nbio_v7_0_pcie_index_data; > @@ -122,7 +122,7 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, > u32 reg) > static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) > { > unsigned long flags, address, data; > - struct nbio_pcie_index_data *nbio_pcie_id; > + const struct nbio_pcie_index_data *nbio_pcie_id; > > if (adev->flags & AMD_IS_APU) > nbio_pcie_id = &nbio_v7_0_pcie_index_data; > -- > 2.9.4 > > _______________________________________________ > mesa-dev mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
