r600_eliminate_fast_color_clear(rctx, rtex);
/* Disable CMASK if flush_resource isn't going
@@ -638,17 +499,10 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
rscreen->ws->buffer_set_metadata(res->buf, &metadata);
}
- if (rscreen->chip_class >= GFX9) {
- offset = rtex->surface.u.gfx9.surf_offset;
- stride = rtex->surface.u.gfx9.surf_pitch *
- rtex->surface.bpe;
- slice_size = rtex->surface.u.gfx9.surf_slice_size;
- } else {
- offset = rtex->surface.u.legacy.level[0].offset;
- stride = rtex->surface.u.legacy.level[0].nblk_x *
- rtex->surface.bpe;
- slice_size = rtex->surface.u.legacy.level[0].slice_size;
- }
+ offset = rtex->surface.u.legacy.level[0].offset;
+ stride = rtex->surface.u.legacy.level[0].nblk_x *
+ rtex->surface.bpe;
+ slice_size = rtex->surface.u.legacy.level[0].slice_size;
} else {
/* Move a suballocated buffer into a non-suballocated
allocation. */
if (rscreen->ws->buffer_is_suballocated(res->buf)) {
@@ -710,8 +564,6 @@ static void r600_texture_destroy(struct pipe_screen *screen,
r600_resource_reference(&rtex->cmask_buffer, NULL);
}
pb_reference(&resource->buf, NULL);
- r600_resource_reference(&rtex->dcc_separate_buffer, NULL);
- r600_resource_reference(&rtex->last_dcc_separate_buffer, NULL);
FREE(rtex);
}
@@ -730,25 +582,17 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
memset(out, 0, sizeof(*out));
- if (rscreen->chip_class >= GFX9) {
- out->alignment = rtex->surface.u.gfx9.fmask_alignment;
- out->size = rtex->surface.u.gfx9.fmask_size;
- return;
- }
-
templ.nr_samples = 1;
flags = rtex->surface.flags | RADEON_SURF_FMASK;
- if (rscreen->chip_class <= CAYMAN) {
- /* Use the same parameters and tile mode. */
- fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
- fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
- fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
- fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
+ /* Use the same parameters and tile mode. */
+ fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
+ fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
+ fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
+ fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
- if (nr_samples <= 4)
- fmask.u.legacy.bankh = 4;
- }
+ if (nr_samples <= 4)
+ fmask.u.legacy.bankh = 4;
switch (nr_samples) {
case 2:
@@ -834,76 +678,15 @@ void r600_texture_get_cmask_info(struct
r600_common_screen *rscreen,
align(slice_bytes, base_align);
}
-static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
- struct r600_texture *rtex,
- struct r600_cmask_info *out)
-{
- unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
- unsigned num_pipes = rscreen->info.num_tile_pipes;
- unsigned cl_width, cl_height;
-
- if (rscreen->chip_class >= GFX9) {
- out->alignment = rtex->surface.u.gfx9.cmask_alignment;
- out->size = rtex->surface.u.gfx9.cmask_size;
- return;
- }
-
- switch (num_pipes) {
- case 2:
- cl_width = 32;
- cl_height = 16;
- break;
- case 4:
- cl_width = 32;
- cl_height = 32;
- break;
- case 8:
- cl_width = 64;
- cl_height = 32;
- break;
- case 16: /* Hawaii */
- cl_width = 64;
- cl_height = 64;
- break;
- default:
- assert(0);
- return;
- }
-
- unsigned base_align = num_pipes * pipe_interleave_bytes;
-
- unsigned width = align(rtex->resource.b.b.width0, cl_width*8);
- unsigned height = align(rtex->resource.b.b.height0, cl_height*8);
- unsigned slice_elements = (width * height) / (8*8);
-
- /* Each element of CMASK is a nibble. */
- unsigned slice_bytes = slice_elements / 2;
-
- out->slice_tile_max = (width * height) / (128*128);
- if (out->slice_tile_max)
- out->slice_tile_max -= 1;
-
- out->alignment = MAX2(256, base_align);
- out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
- align(slice_bytes, base_align);
-}
-
static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
- if (rscreen->chip_class >= SI) {
- si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
- } else {
- r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
- }
+ r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
rtex->size = rtex->cmask.offset + rtex->cmask.size;
- if (rscreen->chip_class >= SI)
- rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
- else
- rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
+ rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
}
static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
@@ -914,11 +697,7 @@ static void r600_texture_alloc_cmask_separate(struct
r600_common_screen *rscreen
assert(rtex->cmask.size == 0);
- if (rscreen->chip_class >= SI) {
- si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
- } else {
- r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
- }
+ r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
rtex->cmask_buffer = (struct r600_resource *)
r600_aligned_buffer_create(&rscreen->b,
@@ -934,10 +713,7 @@ static void r600_texture_alloc_cmask_separate(struct
r600_common_screen *rscreen
/* update colorbuffer state bits */
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
- if (rscreen->chip_class >= SI)
- rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
- else
- rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
+ rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
p_atomic_inc(&rscreen->compressed_colortex_counter);
}
@@ -949,8 +725,6 @@ static void r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = rscreen->info.num_tile_pipes;
- assert(rscreen->chip_class <= VI);
-
rtex->surface.htile_size = 0;
if (rscreen->chip_class <= EVERGREEN &&
@@ -963,22 +737,6 @@ static void r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
rtex->resource.b.b.height0 > 7680))
return;
- /* HTILE is broken with 1D tiling on old kernels and CIK. */
- if (rscreen->chip_class >= CIK &&
- rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
- rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
- return;
-
- /* Overalign HTILE on P2 configs to work around GPU hangs in
- * piglit/depthstencil-render-miplevels 585.
- *
- * This has been confirmed to help Kabini & Stoney, where the hangs
- * are always reproducible. I think I have seen the test hang
- * on Carrizo too, though it was very rare there.
- */
- if (rscreen->chip_class >= CIK && num_pipes < 4)
- num_pipes = 4;
-
switch (num_pipes) {
case 1:
cl_width = 32;
@@ -1023,8 +781,7 @@ static void r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
{
- if (rscreen->chip_class <= VI && !rtex->tc_compatible_htile)
- r600_texture_get_htile_size(rscreen, rtex);
+ r600_texture_get_htile_size(rscreen, rtex);
if (!rtex->surface.htile_size)
return;
@@ -1049,64 +806,6 @@ void r600_print_texture_info(struct r600_common_screen
*rscreen,
rtex->surface.bpe, rtex->resource.b.b.nr_samples,
rtex->surface.flags,
util_format_short_name(rtex->resource.b.b.format));
- if (rscreen->chip_class >= GFX9) {
- u_log_printf(log, " Surf: size=%"PRIu64", slice_size=%"PRIu64",
"
- "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
- rtex->surface.surf_size,
- rtex->surface.u.gfx9.surf_slice_size,
- rtex->surface.surf_alignment,
- rtex->surface.u.gfx9.surf.swizzle_mode,
- rtex->surface.u.gfx9.surf.epitch,
- rtex->surface.u.gfx9.surf_pitch);
-
- if (rtex->fmask.size) {
- u_log_printf(log, " FMASK: offset=%"PRIu64",
size=%"PRIu64", "
- "alignment=%u, swmode=%u, epitch=%u\n",
- rtex->fmask.offset,
- rtex->surface.u.gfx9.fmask_size,
- rtex->surface.u.gfx9.fmask_alignment,
- rtex->surface.u.gfx9.fmask.swizzle_mode,
- rtex->surface.u.gfx9.fmask.epitch);
- }
-
- if (rtex->cmask.size) {
- u_log_printf(log, " CMask: offset=%"PRIu64",
size=%"PRIu64", "
- "alignment=%u, rb_aligned=%u,
pipe_aligned=%u\n",
- rtex->cmask.offset,
- rtex->surface.u.gfx9.cmask_size,
- rtex->surface.u.gfx9.cmask_alignment,
- rtex->surface.u.gfx9.cmask.rb_aligned,
- rtex->surface.u.gfx9.cmask.pipe_aligned);
- }
-
- if (rtex->htile_offset) {
- u_log_printf(log, " HTile: offset=%"PRIu64",
size=%"PRIu64", alignment=%u, "
- "rb_aligned=%u, pipe_aligned=%u\n",
- rtex->htile_offset,
- rtex->surface.htile_size,
- rtex->surface.htile_alignment,
- rtex->surface.u.gfx9.htile.rb_aligned,
- rtex->surface.u.gfx9.htile.pipe_aligned);
- }
-
- if (rtex->dcc_offset) {
- u_log_printf(log, " DCC: offset=%"PRIu64", size=%"PRIu64",
"
- "alignment=%u, pitch_max=%u,
num_dcc_levels=%u\n",
- rtex->dcc_offset, rtex->surface.dcc_size,
- rtex->surface.dcc_alignment,
- rtex->surface.u.gfx9.dcc_pitch_max,
- rtex->surface.num_dcc_levels);
- }
-
- if (rtex->surface.u.gfx9.stencil_offset) {
- u_log_printf(log, " Stencil: offset=%"PRIu64", swmode=%u,
epitch=%u\n",
- rtex->surface.u.gfx9.stencil_offset,
- rtex->surface.u.gfx9.stencil.swizzle_mode,
- rtex->surface.u.gfx9.stencil.epitch);
- }
- return;
- }
-
u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u,
scanout=%u\n",
rtex->surface.surf_size, rtex->surface.surf_alignment,
rtex->surface.u.legacy.bankw,
@@ -1129,22 +828,9 @@ void r600_print_texture_info(struct r600_common_screen
*rscreen,
if (rtex->htile_offset)
u_log_printf(log, " HTile: offset=%"PRIu64", size=%"PRIu64", "
- "alignment=%u, TC_compatible = %u\n",
- rtex->htile_offset, rtex->surface.htile_size,
- rtex->surface.htile_alignment,
- rtex->tc_compatible_htile);
-
- if (rtex->dcc_offset) {
- u_log_printf(log, " DCC: offset=%"PRIu64", size=%"PRIu64",
alignment=%u\n",
- rtex->dcc_offset, rtex->surface.dcc_size,
- rtex->surface.dcc_alignment);
- for (i = 0; i <= rtex->resource.b.b.last_level; i++)
- u_log_printf(log, " DCCLevel[%i]: enabled=%u,
offset=%"PRIu64", "
- "fast_clear_size=%"PRIu64"\n",
- i, i < rtex->surface.num_dcc_levels,
- rtex->surface.u.legacy.level[i].dcc_offset,
-
rtex->surface.u.legacy.level[i].dcc_fast_clear_size);
- }
+ "alignment=%u\n",
+ rtex->htile_offset, rtex->surface.htile_size,
+ rtex->surface.htile_alignment);
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
u_log_printf(log, " Level[%i]: offset=%"PRIu64",
slice_size=%"PRIu64", "
@@ -1208,23 +894,7 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->surface = *surface;
rtex->size = rtex->surface.surf_size;
-
- rtex->tc_compatible_htile = rtex->surface.htile_size != 0 &&
- (rtex->surface.flags &
- RADEON_SURF_TC_COMPATIBLE_HTILE);
-
- /* TC-compatible HTILE:
- * - VI only supports Z32_FLOAT.
- * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
- if (rtex->tc_compatible_htile) {
- if (rscreen->chip_class >= GFX9 &&
- base->format == PIPE_FORMAT_Z16_UNORM)
- rtex->db_render_format = base->format;
- else
- rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
- } else {
- rtex->db_render_format = base->format;
- }
+ rtex->db_render_format = base->format;
/* Tiled depth textures utilize the non-displayable tile order.
* This must be done after r600_setup_surface.
@@ -1233,23 +903,12 @@ r600_texture_create_object(struct pipe_screen *screen,
/* Applies to GCN. */
rtex->last_msaa_resolve_target_micro_mode =
rtex->surface.micro_tile_mode;
- /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
- * between frames, so the only thing that can enable separate DCC
- * with DRI2 is multiple slow clears within a frame.
- */
- rtex->ps_draw_ratio = 0;
-
if (rtex->is_depth) {
if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
rscreen->chip_class >= EVERGREEN) {
- if (rscreen->chip_class >= GFX9) {
- rtex->can_sample_z = true;
- rtex->can_sample_s = true;
- } else {
- rtex->can_sample_z =
!rtex->surface.u.legacy.depth_adjusted;
- rtex->can_sample_s =
!rtex->surface.u.legacy.stencil_adjusted;
- }
+ rtex->can_sample_z =
!rtex->surface.u.legacy.depth_adjusted;
+ rtex->can_sample_s =
!rtex->surface.u.legacy.stencil_adjusted;
} else {
if (rtex->resource.b.b.nr_samples <= 1 &&
(rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM
||
@@ -1276,18 +935,6 @@ r600_texture_create_object(struct pipe_screen *screen,
return NULL;
}
}
-
- /* Shared textures must always set up DCC here.
- * If it's not present, it will be disabled by
- * apply_opaque_metadata later.
- */
- if (rtex->surface.dcc_size &&
- (buf || !(rscreen->debug_flags & DBG_NO_DCC)) &&
- !(rtex->surface.flags & RADEON_SURF_SCANOUT)) {
- /* Reserve space for the DCC buffer. */
- rtex->dcc_offset = align64(rtex->size,
rtex->surface.dcc_alignment);
- rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
- }
}
/* Now create the backing buffer. */
@@ -1324,23 +971,12 @@ r600_texture_create_object(struct pipe_screen *screen,
if (rtex->htile_offset) {
uint32_t clear_value = 0;
- if (rscreen->chip_class >= GFX9 || rtex->tc_compatible_htile)
- clear_value = 0x0000030F;
-
r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
rtex->htile_offset,
rtex->surface.htile_size,
clear_value);
}
- /* Initialize DCC only if the texture is not being imported. */
- if (!buf && rtex->dcc_offset) {
- r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
- rtex->dcc_offset,
- rtex->surface.dcc_size,
- 0xFFFFFFFF);
- }
-
/* Initialize the CMASK base register value. */
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
@@ -1383,14 +1019,6 @@ r600_choose_tiling(struct r600_common_screen *rscreen,
if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
- /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
- * which requires 2D tiling.
- */
- if (rscreen->chip_class == VI &&
- is_depth_stencil &&
- (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY))
- return RADEON_SURF_MODE_2D;
-
/* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources.
*/
if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
(templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
@@ -1411,12 +1039,6 @@ r600_choose_tiling(struct r600_common_screen *rscreen,
if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
- /* Cursors are linear on SI.
- * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
- if (rscreen->chip_class >= SI &&
- (templ->bind & PIPE_BIND_CURSOR))
- return RADEON_SURF_MODE_LINEAR_ALIGNED;
-
if (templ->bind & PIPE_BIND_LINEAR)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
@@ -1449,20 +1071,11 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct radeon_surf surface = {0};
bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
- bool tc_compatible_htile =
- rscreen->chip_class >= VI &&
- (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
- !(rscreen->debug_flags & DBG_NO_HYPERZ) &&
- !is_flushed_depth &&
- templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient
with MSAA */
- util_format_is_depth_or_stencil(templ->format);
-
int r;
r = r600_init_surface(rscreen, &surface, templ,
r600_choose_tiling(rscreen, templ), 0, 0,
- false, false, is_flushed_depth,
- tc_compatible_htile);
+ false, false, is_flushed_depth);
if (r) {
return NULL;
}
@@ -1500,7 +1113,7 @@ static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen *screen
&array_mode, &is_scanout);
r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
- offset, true, is_scanout, false, false);
+ offset, true, is_scanout, false);
if (r) {
return NULL;
}
@@ -2124,114 +1737,6 @@ static void evergreen_set_clear_color(struct
r600_texture *rtex,
memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
}
-/* Set the same micro tile mode as the destination of the last MSAA resolve.
- * This allows hitting the MSAA resolve fast path, which requires that both
- * src and dst micro tile modes match.
- */
-static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
- struct r600_texture *rtex)
-{
- if (rtex->resource.b.is_shared ||
- rtex->resource.b.b.nr_samples <= 1 ||
- rtex->surface.micro_tile_mode ==
rtex->last_msaa_resolve_target_micro_mode)
- return;
-
- assert(rscreen->chip_class >= GFX9 ||
- rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
- assert(rtex->resource.b.b.last_level == 0);
-
- if (rscreen->chip_class >= GFX9) {
- /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
- assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
-
- /* If you do swizzle_mode % 4, you'll get:
- * 0 = Depth
- * 1 = Standard,
- * 2 = Displayable
- * 3 = Rotated
- *
- * Depth-sample order isn't allowed:
- */
- assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
-
- switch (rtex->last_msaa_resolve_target_micro_mode) {
- case RADEON_MICRO_MODE_DISPLAY:
- rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
- rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
- break;
- case RADEON_MICRO_MODE_THIN:
- rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
- rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
- break;
- case RADEON_MICRO_MODE_ROTATED:
- rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
- rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
- break;
- default: /* depth */
- assert(!"unexpected micro mode");
- return;
- }
- } else if (rscreen->chip_class >= CIK) {
- /* These magic numbers were copied from addrlib. It doesn't use
- * any definitions for them either. They are all 2D_TILED_THIN1
- * modes with different bpp and micro tile mode.
- */
- switch (rtex->last_msaa_resolve_target_micro_mode) {
- case RADEON_MICRO_MODE_DISPLAY:
- rtex->surface.u.legacy.tiling_index[0] = 10;
- break;
- case RADEON_MICRO_MODE_THIN:
- rtex->surface.u.legacy.tiling_index[0] = 14;
- break;
- case RADEON_MICRO_MODE_ROTATED:
- rtex->surface.u.legacy.tiling_index[0] = 28;
- break;
- default: /* depth, thick */
- assert(!"unexpected micro mode");
- return;
- }
- } else { /* SI */
- switch (rtex->last_msaa_resolve_target_micro_mode) {
- case RADEON_MICRO_MODE_DISPLAY:
- switch (rtex->surface.bpe) {
- case 1:
- rtex->surface.u.legacy.tiling_index[0] = 10;
- break;
- case 2:
- rtex->surface.u.legacy.tiling_index[0] = 11;
- break;
- default: /* 4, 8 */
- rtex->surface.u.legacy.tiling_index[0] = 12;
- break;
- }
- break;
- case RADEON_MICRO_MODE_THIN:
- switch (rtex->surface.bpe) {
- case 1:
- rtex->surface.u.legacy.tiling_index[0] = 14;
- break;
- case 2:
- rtex->surface.u.legacy.tiling_index[0] = 15;
- break;
- case 4:
- rtex->surface.u.legacy.tiling_index[0] = 16;
- break;
- default: /* 8, 16 */
- rtex->surface.u.legacy.tiling_index[0] = 17;
- break;
- }
- break;
- default: /* depth, thick */
- assert(!"unexpected micro mode");
- return;
- }
- }
-
- rtex->surface.micro_tile_mode =
rtex->last_msaa_resolve_target_micro_mode;
-
- p_atomic_inc(&rscreen->dirty_tex_counter);
-}
-
void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
struct pipe_framebuffer_state *fb,
struct r600_atom *fb_state,
@@ -2285,24 +1790,12 @@ void evergreen_do_fast_color_clear(struct
r600_common_context *rctx,
!(tex->resource.external_usage &
PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
continue;
- /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
- if (rctx->chip_class == CIK &&
- tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D
&&
- rctx->screen->info.drm_major == 2 &&
- rctx->screen->info.drm_minor < 38) {
- continue;
- }
-
{
/* 128-bit formats are unusupported */
if (tex->surface.bpe > 8) {
continue;
}
- /* RB+ doesn't work with CMASK fast clear on Stoney. */
- if (rctx->family == CHIP_STONEY)
- continue;
-
/* ensure CMASK is enabled */
r600_texture_alloc_cmask_separate(rctx->screen, tex);
if (tex->cmask.size == 0) {
@@ -2322,10 +1815,6 @@ void evergreen_do_fast_color_clear(struct
r600_common_context *rctx,
p_atomic_inc(&rctx->screen->compressed_colortex_counter);
}
- /* We can change the micro tile mode before a full clear. */
- if (rctx->screen->chip_class >= SI)
- si_set_optimal_micro_tile_mode(rctx->screen, tex);
-
evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
if (dirty_cbufs)
@@ -2425,7 +1914,7 @@ r600_texture_from_memobj(struct pipe_screen *screen,
r = r600_init_surface(rscreen, &surface, templ,
array_mode, memobj->stride,
offset, true, is_scanout,
- false, false);
+ false);
if (r)
return NULL;
diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c
index 28551e2..ca4248a 100644
--- a/src/gallium/drivers/r600/r600_uvd.c
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -162,7 +162,7 @@ static struct pb_buffer* r600_uvd_set_dtb(struct ruvd_msg
*msg, struct vl_video_
msg->body.decode.dt_field_mode = buf->base.interlaced;
msg->body.decode.dt_surf_tile_config |=
RUVD_NUM_BANKS(eg_num_banks(rscreen->b.info.r600_num_banks));
- ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface, RUVD_SURFACE_TYPE_LEGACY);
+ ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
return luma->resource.buf;
}
diff --git a/src/gallium/drivers/r600/radeon_uvd.c
b/src/gallium/drivers/r600/radeon_uvd.c
index fabc73e..b0551d7 100644
--- a/src/gallium/drivers/r600/radeon_uvd.c
+++ b/src/gallium/drivers/r600/radeon_uvd.c
@@ -205,8 +205,7 @@ static uint32_t profile2stream_type(struct ruvd_decoder
*dec, unsigned family)
{
switch (u_reduce_video_profile(dec->base.profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- return (family >= CHIP_TONGA) ?
- RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
+ return RUVD_CODEC_H264;
case PIPE_VIDEO_FORMAT_VC1:
return RUVD_CODEC_VC1;
@@ -229,60 +228,6 @@ static uint32_t profile2stream_type(struct ruvd_decoder
*dec, unsigned family)
}
}
-static unsigned calc_ctx_size_h264_perf(struct ruvd_decoder *dec)
-{
- unsigned width_in_mb, height_in_mb, ctx_size;
- unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
- unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
-
- unsigned max_references = dec->base.max_references + 1;
-
- // picture width & height in 16 pixel units
- width_in_mb = width / VL_MACROBLOCK_WIDTH;
- height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
-
- if (!dec->use_legacy) {
- unsigned fs_in_mb = width_in_mb * height_in_mb;
- unsigned num_dpb_buffer;
- switch(dec->base.level) {
- case 30:
- num_dpb_buffer = 8100 / fs_in_mb;
- break;
- case 31:
- num_dpb_buffer = 18000 / fs_in_mb;
- break;
- case 32:
- num_dpb_buffer = 20480 / fs_in_mb;
- break;
- case 41:
- num_dpb_buffer = 32768 / fs_in_mb;
- break;
- case 42:
- num_dpb_buffer = 34816 / fs_in_mb;
- break;
- case 50:
- num_dpb_buffer = 110400 / fs_in_mb;
- break;
- case 51:
- num_dpb_buffer = 184320 / fs_in_mb;
- break;
- default:
- num_dpb_buffer = 184320 / fs_in_mb;
- break;
- }
- num_dpb_buffer++;
- max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer),
max_references);
- ctx_size = max_references * align(width_in_mb * height_in_mb *
192, 256);
- } else {
- // the firmware seems to always assume a minimum of ref frames
- max_references = MAX2(NUM_H264_REFS, max_references);
- // macroblock context buffer
- ctx_size = align(width_in_mb * height_in_mb * max_references *
192, 256);
- }
-
- return ctx_size;
-}
-
static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
{
unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
@@ -335,10 +280,7 @@ static unsigned calc_ctx_size_h265_main10(struct
ruvd_decoder *dec, struct pipe_
static unsigned get_db_pitch_alignment(struct ruvd_decoder *dec)
{
- if (((struct r600_common_screen*)dec->screen)->family < CHIP_VEGA10)
- return 16;
- else
- return 32;
+ return 16;
}
/* calculate size of reference picture buffer */
@@ -399,8 +341,7 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
num_dpb_buffer++;
max_references = MAX2(MIN2(NUM_H264_REFS,
num_dpb_buffer), max_references);
dpb_size = image_size * max_references;
- if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
- (((struct r600_common_screen*)dec->screen)->family
< CHIP_POLARIS10)) {
+ if ((dec->stream_type != RUVD_CODEC_H264_PERF)) {
dpb_size += max_references * align(width_in_mb
* height_in_mb * 192, alignment);
dpb_size += align(width_in_mb * height_in_mb *
32, alignment);
}
@@ -409,8 +350,7 @@ static unsigned calc_dpb_size(struct ruvd_decoder *dec)
max_references = MAX2(NUM_H264_REFS, max_references);
// reference picture buffer
dpb_size = image_size * max_references;
- if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
- (((struct r600_common_screen*)dec->screen)->family
< CHIP_POLARIS10)) {
+ if ((dec->stream_type != RUVD_CODEC_H264_PERF)) {
// macroblock context buffer
dpb_size += width_in_mb * height_in_mb *
max_references * 192;
// IT surface buffer
@@ -610,8 +550,6 @@ static struct ruvd_h265 get_h265_msg(struct ruvd_decoder
*dec, struct pipe_video
result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag
<< 6;
result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag
<< 7;
result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
- if (((struct r600_common_screen*)dec->screen)->family == CHIP_CARRIZO)
- result.sps_info_flags |= 1 << 9;
if (pic->UseRefPicList == true)
result.sps_info_flags |= 1 << 10;
@@ -1250,13 +1188,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
dec->msg->body.decode.bsd_size = bs_size;
dec->msg->body.decode.db_pitch = align(dec->base.width,
get_db_pitch_alignment(dec));
- if (dec->stream_type == RUVD_CODEC_H264_PERF &&
- ((struct r600_common_screen*)dec->screen)->family >= CHIP_POLARIS10)
- dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
-
dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
- if (((struct r600_common_screen*)dec->screen)->family >= CHIP_STONEY)
- dec->msg->body.decode.dt_wa_chroma_top_offset =
dec->msg->body.decode.dt_pitch / 2;
switch (u_reduce_video_profile(picture->profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
@@ -1407,8 +1339,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct
pipe_context *context,
goto error;
}
- dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
- FB_BUFFER_SIZE;
+ dec->fb_size = FB_BUFFER_SIZE;
bs_buf_size = width * height * (512 / (16 * 16));
for (i = 0; i < NUM_BUFFERS; ++i) {
unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
@@ -1440,36 +1371,10 @@ struct pipe_video_codec *ruvd_create_decoder(struct
pipe_context *context,
rvid_clear_buffer(context, &dec->dpb);
}
- if (dec->stream_type == RUVD_CODEC_H264_PERF && info.family >= CHIP_POLARIS10) {
- unsigned ctx_size = calc_ctx_size_h264_perf(dec);
- if (!rvid_create_buffer(dec->screen, &dec->ctx, ctx_size,
PIPE_USAGE_DEFAULT)) {
- RVID_ERR("Can't allocated context buffer.\n");
- goto error;
- }
- rvid_clear_buffer(context, &dec->ctx);
- }
-
- if (info.family >= CHIP_POLARIS10 && info.drm_minor >= 3) {
- if (!rvid_create_buffer(dec->screen, &dec->sessionctx,
- UVD_SESSION_CONTEXT_SIZE,
- PIPE_USAGE_DEFAULT)) {
- RVID_ERR("Can't allocated session ctx.\n");
- goto error;
- }
- rvid_clear_buffer(context, &dec->sessionctx);
- }
-
- if (info.family >= CHIP_VEGA10) {
- dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
- dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
- dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
- dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
- } else {
- dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0;
- dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1;
- dec->reg.cmd = RUVD_GPCOM_VCPU_CMD;
- dec->reg.cntl = RUVD_ENGINE_CNTL;
- }
+ dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0;
+ dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1;
+ dec->reg.cmd = RUVD_GPCOM_VCPU_CMD;
+ dec->reg.cntl = RUVD_ENGINE_CNTL;
map_msg_fb_it_buf(dec);
dec->msg->size = sizeof(*dec->msg);
@@ -1506,20 +1411,10 @@ error:
}
/* calculate top/bottom offset */
-static unsigned texture_offset(struct radeon_surf *surface, unsigned layer,
- enum ruvd_surface_type type)
+static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
{
- switch (type) {
- default:
- case RUVD_SURFACE_TYPE_LEGACY:
- return surface->u.legacy.level[0].offset +
- layer * surface->u.legacy.level[0].slice_size;
- break;
- case RUVD_SURFACE_TYPE_GFX9:
- return surface->u.gfx9.surf_offset +
- layer * surface->u.gfx9.surf_slice_size;
- break;
- }
+ return surface->u.legacy.level[0].offset +
+ layer * surface->u.legacy.level[0].slice_size;
}
/* hw encode the aspect of macro tiles */
@@ -1552,67 +1447,46 @@ static unsigned bank_wh(unsigned bankwh)
* fill decoding target field from the luma and chroma surfaces
*/
void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
- struct radeon_surf *chroma, enum ruvd_surface_type type)
+ struct radeon_surf *chroma)
{
- switch (type) {
+ msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x *
luma->blk_w;
+ switch (luma->u.legacy.level[0].mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
+ msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
+ break;
+ case RADEON_SURF_MODE_1D:
+ msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
+ msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
+ break;
+ case RADEON_SURF_MODE_2D:
+ msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
+ msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
+ break;
default:
- case RUVD_SURFACE_TYPE_LEGACY:
- msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x *
luma->blk_w;
- switch (luma->u.legacy.level[0].mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
- msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
- break;
- case RADEON_SURF_MODE_1D:
- msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
- msg->body.decode.dt_array_mode =
RUVD_ARRAY_MODE_1D_THIN;
- break;
- case RADEON_SURF_MODE_2D:
- msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
- msg->body.decode.dt_array_mode =
RUVD_ARRAY_MODE_2D_THIN;
- break;
- default:
- assert(0);
- break;
- }
+ assert(0);
+ break;
+ }
- msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
+ msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0);
+ if (chroma)
+ msg->body.decode.dt_chroma_top_offset = texture_offset(chroma,
0);
+ if (msg->body.decode.dt_field_mode) {
+ msg->body.decode.dt_luma_bottom_offset = texture_offset(luma,
1);
if (chroma)
- msg->body.decode.dt_chroma_top_offset =
texture_offset(chroma, 0, type);
- if (msg->body.decode.dt_field_mode) {
- msg->body.decode.dt_luma_bottom_offset =
texture_offset(luma, 1, type);
- if (chroma)
- msg->body.decode.dt_chroma_bottom_offset =
texture_offset(chroma, 1, type);
- } else {
- msg->body.decode.dt_luma_bottom_offset =
msg->body.decode.dt_luma_top_offset;
- msg->body.decode.dt_chroma_bottom_offset =
msg->body.decode.dt_chroma_top_offset;
- }
-
- if (chroma) {
- assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
- assert(luma->u.legacy.bankh == chroma->u.legacy.bankh);
- assert(luma->u.legacy.mtilea ==
chroma->u.legacy.mtilea);
- }
+ msg->body.decode.dt_chroma_bottom_offset =
texture_offset(chroma, 1);
+ } else {
+ msg->body.decode.dt_luma_bottom_offset =
msg->body.decode.dt_luma_top_offset;
+ msg->body.decode.dt_chroma_bottom_offset =
msg->body.decode.dt_chroma_top_offset;
+ }
- msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
- msg->body.decode.dt_surf_tile_config |=
RUVD_BANK_HEIGHT(bank_wh(luma->u.legacy.bankh));
- msg->body.decode.dt_surf_tile_config |=
RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
- break;
- case RUVD_SURFACE_TYPE_GFX9:
- msg->body.decode.dt_pitch = luma->u.gfx9.surf_pitch *
luma->blk_w;
- /* SWIZZLE LINEAR MODE */
- msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
- msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
- msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0,
type);
- msg->body.decode.dt_chroma_top_offset = texture_offset(chroma,
0, type);
- if (msg->body.decode.dt_field_mode) {
- msg->body.decode.dt_luma_bottom_offset =
texture_offset(luma, 1, type);
- msg->body.decode.dt_chroma_bottom_offset =
texture_offset(chroma, 1, type);
- } else {
- msg->body.decode.dt_luma_bottom_offset =
msg->body.decode.dt_luma_top_offset;
- msg->body.decode.dt_chroma_bottom_offset =
msg->body.decode.dt_chroma_top_offset;
- }
- msg->body.decode.dt_surf_tile_config = 0;
- break;
+ if (chroma) {
+ assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
+ assert(luma->u.legacy.bankh == chroma->u.legacy.bankh);
+ assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
}
+
+ msg->body.decode.dt_surf_tile_config |=
RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
+ msg->body.decode.dt_surf_tile_config |=
RUVD_BANK_HEIGHT(bank_wh(luma->u.legacy.bankh));
+ msg->body.decode.dt_surf_tile_config |=
RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
}
diff --git a/src/gallium/drivers/r600/radeon_uvd.h
b/src/gallium/drivers/r600/radeon_uvd.h
index a927c84..c371b14 100644
--- a/src/gallium/drivers/r600/radeon_uvd.h
+++ b/src/gallium/drivers/r600/radeon_uvd.h
@@ -117,11 +117,6 @@
#define RUVD_VC1_PROFILE_MAIN 0x00000001
#define RUVD_VC1_PROFILE_ADVANCED 0x00000002
-enum ruvd_surface_type {
- RUVD_SURFACE_TYPE_LEGACY = 0,
- RUVD_SURFACE_TYPE_GFX9
-};
-
struct ruvd_mvc_element {
uint16_t viewOrderIndex;
uint16_t viewId;
@@ -443,5 +438,5 @@ struct pipe_video_codec *ruvd_create_decoder(struct
pipe_context *context,
/* fill decoding target field from the luma and chroma surfaces */
void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
- struct radeon_surf *chroma, enum ruvd_surface_type
type);
+ struct radeon_surf *chroma);
#endif
diff --git a/src/gallium/drivers/r600/radeon_vce.c
b/src/gallium/drivers/r600/radeon_vce.c
index e8b1a63..16a0127 100644
--- a/src/gallium/drivers/r600/radeon_vce.c
+++ b/src/gallium/drivers/r600/radeon_vce.c
@@ -225,16 +225,10 @@ struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
signed *luma_offset, signed *chroma_offset)
{
- struct r600_common_screen *rscreen = (struct r600_common_screen
*)enc->screen;
unsigned pitch, vpitch, fsize;
- if (rscreen->chip_class < GFX9) {
- pitch = align(enc->luma->u.legacy.level[0].nblk_x *
enc->luma->bpe, 128);
- vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
- } else {
- pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe,
256);
- vpitch = align(enc->luma->u.gfx9.surf_height, 16);
- }
+ pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe,
128);
+ vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
fsize = pitch * (vpitch + vpitch / 2);
*luma_offset = slot->index * fsize;
@@ -420,16 +414,6 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
rscreen->info.drm_major == 3)
enc->use_vui = true;
- if (rscreen->info.family >= CHIP_TONGA &&
- rscreen->info.family != CHIP_STONEY &&
- rscreen->info.family != CHIP_POLARIS11 &&
- rscreen->info.family != CHIP_POLARIS12)
- enc->dual_pipe = true;
- /* TODO enable B frame with dual instance */
- if ((rscreen->info.family >= CHIP_TONGA) &&
- (templ->max_references == 1) &&
- (rscreen->info.vce_harvest_config == 0))
- enc->dual_inst = true;
enc->base = *templ;
enc->base.context = context;
@@ -466,12 +450,8 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
- cpb_size = (rscreen->chip_class < GFX9) ?
- align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
- align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
-
- align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
- align(tmp_surf->u.gfx9.surf_height, 32);
+ cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe,
128) *
+ align(tmp_surf->u.legacy.level[0].nblk_y, 32);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
diff --git a/src/gallium/drivers/r600/radeon_video.c
b/src/gallium/drivers/r600/radeon_video.c
index 99b6676..c7acc3d 100644
--- a/src/gallium/drivers/r600/radeon_video.c
+++ b/src/gallium/drivers/r600/radeon_video.c
@@ -156,13 +156,11 @@ void rvid_join_surfaces(struct r600_common_context *rctx,
if (!surfaces[i])
continue;
- if (rctx->chip_class < GFX9) {
- /* choose the smallest bank w/h for now */
- wh = surfaces[i]->u.legacy.bankw *
surfaces[i]->u.legacy.bankh;
- if (wh < best_wh) {
- best_wh = wh;
- best_tiling = i;
- }
+ /* choose the smallest bank w/h for now */
+ wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
+ if (wh < best_wh) {
+ best_wh = wh;
+ best_tiling = i;
}
}
@@ -173,17 +171,14 @@ void rvid_join_surfaces(struct r600_common_context *rctx,
/* adjust the texture layer offsets */
off = align(off, surfaces[i]->surf_alignment);
- if (rctx->chip_class < GFX9) {
- /* copy the tiling parameters */
- surfaces[i]->u.legacy.bankw =
surfaces[best_tiling]->u.legacy.bankw;
- surfaces[i]->u.legacy.bankh =
surfaces[best_tiling]->u.legacy.bankh;
- surfaces[i]->u.legacy.mtilea =
surfaces[best_tiling]->u.legacy.mtilea;
- surfaces[i]->u.legacy.tile_split =
surfaces[best_tiling]->u.legacy.tile_split;
+ /* copy the tiling parameters */
+ surfaces[i]->u.legacy.bankw =
surfaces[best_tiling]->u.legacy.bankw;
+ surfaces[i]->u.legacy.bankh =
surfaces[best_tiling]->u.legacy.bankh;
+ surfaces[i]->u.legacy.mtilea =
surfaces[best_tiling]->u.legacy.mtilea;
+ surfaces[i]->u.legacy.tile_split =
surfaces[best_tiling]->u.legacy.tile_split;
- for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
- surfaces[i]->u.legacy.level[j].offset += off;
- } else
- surfaces[i]->u.gfx9.surf_offset += off;
+ for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
+ surfaces[i]->u.legacy.level[j].offset += off;
off += surfaces[i]->surf_size;
}
@@ -237,9 +232,9 @@ int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
- return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
+ return 2048;
case PIPE_VIDEO_CAP_MAX_HEIGHT:
- return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
+ return 1152;
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
@@ -249,7 +244,7 @@ int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_STACKED_FRAMES:
- return (rscreen->family < CHIP_TONGA) ? 1 : 2;
+ return 1;
default:
return 0;
}
@@ -264,40 +259,22 @@ int rvid_get_video_param(struct pipe_screen *screen,
/* no support for MPEG4 on older hw */
return rscreen->family >= CHIP_PALM;
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- if ((rscreen->family == CHIP_POLARIS10 ||
- rscreen->family == CHIP_POLARIS11) &&
- info.uvd_fw_version < UVD_FW_1_66_16 ) {
- RVID_ERR("POLARIS10/11 firmware version need to be
updated.\n");
- return false;
- }
return true;
case PIPE_VIDEO_FORMAT_VC1:
return true;
case PIPE_VIDEO_FORMAT_HEVC:
- /* Carrizo only supports HEVC Main */
- if (rscreen->family >= CHIP_STONEY)
- return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN
||
- profile ==
PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
- else if (rscreen->family >= CHIP_CARRIZO)
- return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
return false;
case PIPE_VIDEO_FORMAT_JPEG:
- if (rscreen->family < CHIP_CARRIZO || rscreen->family
>= CHIP_VEGA10)
- return false;
- if (!(rscreen->info.drm_major == 3 &&
rscreen->info.drm_minor >= 19)) {
- RVID_ERR("No MJPEG support for the kernel
version\n");
- return false;
- }
- return true;
+ return false;
default:
return false;
}
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
- return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
+ return 2048;
case PIPE_VIDEO_CAP_MAX_HEIGHT:
- return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
+ return 1152;
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
return PIPE_FORMAT_P016;
@@ -342,7 +319,7 @@ int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
- return (rscreen->family < CHIP_TONGA) ? 41 : 52;
+ return 41;
case PIPE_VIDEO_PROFILE_HEVC_MAIN:
case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
return 186;
